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DRV8804PWP Datasheet(PDF) 3 Page - Texas Instruments |
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DRV8804PWP Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 27 page  1 2 3 4 5 6 7 8 9 10 14 13 12 11 15 16 17 18 19 20 nFAULT SDATOUT SDATIN SCLK GND GND GND LATCH NC RESET OUT4 nENBL GND OUT3 GND GND OUT1 OUT2 VM VCLAMP 1 2 3 4 5 6 7 8 10 9 11 12 13 14 15 16 nFAULT SDATOUT SDATIN SCLK GND LATCH NC RESET nENBL OUT3 OUT4 GND OUT1 OUT2 VM VCLAMP GND DRV8804 www.ti.com SLVSAW4F – JULY 2011 – REVISED DECEMBER 2015 5 Pin Configuration and Functions DW (Wide SOIC) Package PWP (HTSSOP) 20-Pin Package 16-Pin Package Top View Top View Pin Functions PIN EXTERNAL COMPONENTS I/O(1) DESCRIPTION OR CONNECTIONS NAME SOIC HTSSOP POWER AND GROUND 5, 6, 7, 5, 12, GND — Device ground All pins must be connected to GND. 14, 15, 16 PPAD VM 1 1 — Device power supply Connect to motor supply (8.2 V - 60 V). CONTROL Rising edge latches shift register to output LATCH 13 11 I Latch input stage – internal pulldown nENBL 10 8 I Enable input Active low enables outputs – internal pulldown Active-high reset input initializes internal RESET 11 9 I Reset input logic – internal pulldown SCLK 17 13 I Serial clock Serial clock input – internal pulldown SDATIN 18 14 I Serial data input Serial data input – internal pulldown Serial data output; push-pull structure; see SDATOUT 19 15 O Serial data output serial interface section for details STATUS Logic low when in fault condition nFAULT 20 16 OD Fault (overtemperature, overcurrent) OUTPUT OUT1 3 3 O Output 1 Connect to load 1 OUT2 4 4 O Output 2 Connect to load 2 OUT3 8 6 O Output 3 Connect to load 3 OUT4 9 7 O Output 4 Connect to load 4 Connect to VM supply, or zener diode to VM VCLAMP 2 2 — Output clamp voltage supply (1) Directions: I = input, O = output, OD = open-drain output Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: DRV8804 |
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