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TE3-MUX Datasheet(PDF) 9 Page - Infineon Technologies AG |
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TE3-MUX Datasheet(HTML) 9 Page - Infineon Technologies AG |
9 / 211 page PEB 3445 E List of Figures Page Data Sheet 9 2001-06-29 Figure 1 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 2 Typical DS3 Channelized Application . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 5 Local Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 6 Remote Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 7 Tributary Mapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 8 Tributary Mapper (Transmit Direction) . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 9 Tributary Mapper (Receive Direction) . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 10 Interrupt Driven Reception Sequence Example (32-byte Receive Thresh- old) 56 Figure 11 Interrupt Driven Transmit Sequence Example . . . . . . . . . . . . . . . . . . . 57 Figure 12 DMA Supported Receive Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 13 DMA supported Transmit Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 14 Test Unit Access Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 15 Pattern Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 16 Intel Bus Mode (Demultiplexed Bus Operation) . . . . . . . . . . . . . . . . . . 64 Figure 17 Intel Bus Mode (Multiplexed Bus Operation) . . . . . . . . . . . . . . . . . . . . 64 Figure 18 Motorola Bus Mode (Demultiplexed Bus Operation) . . . . . . . . . . . . . . 66 Figure 19 Motorola Bus Mode (Multiplexed Bus Operation) . . . . . . . . . . . . . . . . 66 Figure 20 Receive Overhead Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Figure 21 Transmit Overhead Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 22 Block Diagram of Test Access Port and Boundary Scan Unit . . . . . . . 70 Figure 23 Input/Output Waveform for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . 184 Figure 24 Intel Demultiplexed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Figure 25 Intel Multiplexed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Figure 26 Read, Write Control Interval in Demultiplexed Bus Mode . . . . . . . . . 187 Figure 27 Read, Write Control Interval in Multiplexed Bus Mode . . . . . . . . . . . 187 Figure 28 Motorola Demultiplexed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . 188 Figure 29 Motorola Multiplexed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Figure 30 Read, Write Control Interval in Demultiplexed Bus Mode . . . . . . . . . 190 Figure 31 Read, Write, ALE Control Interval in Multiplexed Bus Mode . . . . . . . 190 Figure 32 DMA Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Figure 33 DMA Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Figure 34 Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Figure 35 DS3 Transmit Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Figure 36 DS3 Transmit Data Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Figure 37 DS3 Receive Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Figure 38 DS3 Transmit Overhead Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Figure 39 DS3 Transmit Overhead Synchronization Timing . . . . . . . . . . . . . . . 196 Figure 40 DS3 Receive Overhead Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Figure 41 DS3 Transmit Stuff Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 |
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