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S2060A Datasheet(PDF) 2 Page - Applied Micro Circuits Corporation |
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S2060A Datasheet(HTML) 2 Page - Applied Micro Circuits Corporation |
2 / 22 page 2 S2060 GIGABIT ETHERNET TRANSCEIVER March 7, 2001 / Revision H S2060 OVERVIEW The S2060 transmitter and receiver provide serial- ization and deserialization functions for block en- coded data to implement a Gigabit Ethernet interface. The S2060 functional block diagram is de- picted in Figure 2. The sequence of operations is as follows: Transmitter 1.10-bit parallel input 2. Parallel-to-serial conversion 3. Serial output Receiver 1. Clock and data recovery from serial input 2. Serial-to-parallel conversion 3. Frame detection 4. 10-bit parallel output The 10-bit parallel data input to the S2060 should be from a DC-balanced encoding scheme, such as the 8B/10B transmission code, in which information to be transmitted is encoded 8 bits at a time into 10-bit trans- mission characters1. For reference, Table 1 shows the mapping of the parallel data to the 8B/10B codes. Loop Back Local loopback provides a capability for performing off-line testing. This is useful for ensuring the integ- rity of the serial channel before enabling the trans- mission medium. It also allows for system diagnostics. Figure 2. Functional Block Diagram e t y B a t a D ] 9 : 0 [ X R r o ] 9 : 0 [ X T 0123456789 B 0 1 / B 8 n o it a t n e s e r p e R c it e b a h p l A a b c d ei f g hj Table 1. Data Mapping to 8B/10B Alphabetic Representation 1. A.X. Widmer and P.A. Franaszek, "A Byte Oriented DC Bal- anced (0,4) 8B/10B Transmission Code," IBM Research Report RC 9391, May 1982. FIFO (4 x 10) Shift Register 10 10 PLL Clock Recovery w/ lock detect Shift Register D Control Logic COMMA Detect Logic DQ 10 TX[0:9] TBC RXP RXN EWRAP -LCK_REF EN_CDET RBC0 RBC1 COM_DET RX[0:9] TXN TXP S2060 RATEN 2:1 PLL Clock Multiplier w/ lock detect F0 = F1 x 10 |
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