S2060D datasheet(4/22 Pages) AMCC | GIGABIT ETHERNET TRANSCEIVER

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S2060D Datasheet(PDF) 4 Page - Applied Micro Circuits Corporation

Part #	S2060D

Description	GIGABIT ETHERNET TRANSCEIVER

Download	22 Pages

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Manufacturer	AMCC [Applied Micro Circuits Corporation]

Direct Link	http://www.amcc.com

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S2060

GIGABIT ETHERNET TRANSCEIVER

March 7, 2001 / Revision H

RECEIVER DESCRIPTION

Whenever a signal is present, the receiver attempts

to recover the serial clock from the received data

stream. The S2060 searches the serial bit stream for

the occurrence of a positive polarity COMMA sync

pattern (0011111xxx positive running disparity) to

perform word synchronization. Once synchronization

on both bit and word boundaries is achieved, the

receiver provides the decoded data on its parallel

outputs.

Clock Recovery Function

Clock recovery is performed on the input data

stream. A simple state machine in the clock recovery

macro decides whether to acquire lock from the se-

rial data input or from the reference clock. The deci-

sion is based upon the frequency and run length of

the input serial data.

The lock to reference frequency criteria ensure that

the S2060 will respond to variations in the serial data

input frequency (as compared to the reference fre-

quency). The new lock state is dependent upon the

current lock state, as shown in Table 3. The run-

length criteria ensure that the S2060 will respond ap-

propriately and quickly to a loss of signal. The run-

length checker flags a condition of consecutive ones

or zeros across 12 parallel words. Thus, 119 or less

consecutive ones or zeros does not cause signal loss,

129 or more causes signal loss, and 120 – 128 may

or may not, depending on how the data aligns across

byte boundaries. If both the off-frequency detect test

and the run-length test is satisfied, the CRU will at-

tempt to lock to the incoming data.

In any transfer of PLL control between the serial

data and the reference clock, the RBC0 and RBC1

remain phase continuous and glitch free, assuring

the integrity of downstream clocking.

Reference Clock Input

The reference clock must be provided from a low

jitter clock source. The frequency of the received

data stream must be within 400 ppm of the reference

clock to ensure reliable locking of the receiver PLL.

A single reference clock is provided to both the

transmit and receive PLL's.

Data Output

The S2060 provides either framed or unframed par-

allel output data, determined by the state of

EN_CDET. With EN_CDET held ACTIVE, the S2060

will detect and align to the 8B/10B COMMA

codeword anywhere in the data stream. When

EN_CDET is INACTIVE, no attempt is made to syn-

chronize on any particular incoming character. The

S2060 will achieve bit synchronization within 250 bit

times and begin to deliver unframed parallel output

data words whenever it has received full transmis-

sion words. Upon change of state of the EN_CDET

input, the COM_DET output response will be de-

layed by a maximum of 3 byte times.

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Table 3. Lock to Reference Frequency Criteria

Similar Part No. - S2060D

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