K6E0808C1E-C/E-L, K6E0808C1E-I/E-P

CMOS SRAM

Revision 2.0

- 4 -

Feburary 1999

For Cisco

TEST CONDITIONS

* The above test conditions are also applied at industrial temperature range.

Parameter

Value

Input Pulse Levels

0V to 3V

Input Rise and Fall Times

3ns

Input and Output timing Reference Levels

1.5V

Output Loads

See below

Output Loads(A)

Output Loads(B)

5pF*

480

Ω

255

Ω

+5.0V

READ CYCLE*

* The above parameters are also guaranteed at industrial temperature range

.

Parameter

Symbol

K6E0808C1E-10

K6E0808C1E-12

K6E0808C1E-15

Unit

Min

Max

Min

Max

Min

Max

Read Cycle Time

10

-

12

-

15

-

ns

Address Access Time

-

10

-

12

-

15

ns

Chip Select to Output

-

10

-

12

-

15

ns

Output Enable to Valid Output

-

5

-

6

-

7

ns

Chip Enable to Low-Z Output

3

-

3

-

3

-

ns

Output Enable to Low-Z Output

0

-

0

-

0

-

ns

Chip Disable to High-Z Output

0

5

0

6

0

7

ns

Output Disable to High-Z Output

0

5

0

6

0

7

ns

Output Hold from Address Change

3

-

3

-

3

-

ns

Chip Selection to Power Up Time

0

-

0

-

0

-

ns

Chip Selection to Power DownTime

-

10

-

12

-

15

ns

30pF*

480

Ω

255

Ω

+5V

* Including Scope and Jig Capacitance