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PE4314A-Z Datasheet(PDF) 7 Page - Peregrine Semiconductor |
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PE4314A-Z Datasheet(HTML) 7 Page - Peregrine Semiconductor |
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7 / 27 page  PE4314 RF Digital Step Attenuator DOC-67244-4 – (03/2016) Page 7 www.psemi.com Programming Options Parallel/Serial Selection Either a Parallel or Serial interface can be used to control the PE4314. The P/S bit provides this selection, with P/S = LOW selecting the Parallel interface and P/S = HIGH selecting the Serial interface. Parallel Mode Interface The Parallel interface consists of six CMOS- compatible control lines that select the desired attenu- ation state, as shown in Table 5. The Parallel interface timing requirements are defined by Figure 3, Table 8 and switching time in Table 3. For Latched Parallel programming, the latched enable (LE) should be held LOW while changing attenuation state control values, then pulsed LE HIGH to LOW (per Figure 3) to latch new attenuation state into the device. For Direct Parallel programming, the LE line should be pulled HIGH. Changing attenuation state control values will change device state to new attenuation. Direct mode is ideal for manual control of the device (using hardwire, switches or jumpers). In Parallel mode, DATA and CLOCK (CLK) pins are “don’t care” and may be tied to logic LOW or logic HIGH. Serial Interface The Serial interface is a 6-bit Serial-in, Parallel-out shift register buffered by a transparent latch. It is controlled by using three CMOS-compatible signals: DATA, CLK and LE. The DATA and CLK inputs allow data to be serially entered into the shift register, a process that is independent of the state of the LE input. Serial data is clocked in MSB first. The LE input controls the latch. When LE is HIGH, the latch is transparent and the contents of the Serial shift register control the attenuator. When LE is brought LOW, data in the shift register is latched. The shift register must be loaded while LE is held LOW to prevent the attenuator value from changing as data is entered. The LE input should then be toggled HIGH and brought LOW again, latching the new data into the DSA. The Serial timing for the operation is defined by Figure 2 and Table 7. Power-up Control Settings The PE4314 always assumes a specifiable attenu- ation setting on power up. This feature exists for both the Serial and Parallel modes of operation, and allows a known attenuation state to be established before an initial Serial or Parallel control word is provided. When the attenuator powers up in Serial mode (P/S = 1), the six control bits are set to whatever data is present on the six Parallel data inputs (C0.5–C16). This allows any one of the 64 attenuation settings to be specified as the power-up state. When the attenuator powers up in Parallel mode (P/S = 0) with LE = 0, the control bits are automati- cally set to one of four possible values. These four values are selected by the two power-up (PUP) control bits, PUP1 and PUP2, as shown in Table 6. Figure 2 • Serial Interface Timing Diagram Figure 3 • Parallel Interface Timing Diagram tSDHLD tLESUP tLEPW tSDSUP LE Clock Data MSB LSB tPDSUP tPDHLD tLEPW LE Parallel Data C16:C0.5 |
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