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PE43711 Datasheet(PDF) 8 Page - Peregrine Semiconductor |
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PE43711 Datasheet(HTML) 8 Page - Peregrine Semiconductor |
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8 / 31 page  PE43711 UltraCMOS® RF Digital Step Attenuator Page 8 DOC-44414-2 – (3/2015) www.psemi.com Programming Options Parallel/Serial Selection Either a Parallel or Serial interface can be used to control the PE43711. The P/S bit provides this selection, with P/S = LOW selecting the Parallel interface and P/S = HIGH selecting the Serial interface. Parallel Mode Interface The Parallel interface consists of seven CMOS- compatible control lines that select the desired attenu- ation state, as shown in Table 4. The Parallel interface timing requirements are defined by Figure 4 (Parallel Interface Timing Diagram), Table 8 (Parallel and Direct Interface AC Character- istics) and switching time (Table 3). For Latched Parallel programming, the Latch Enable (LE) should be held LOW while changing attenuation state control values then pulse LE HIGH to LOW (per Figure 4) to latch new attenuation state into the device. For Direct Parallel programming, the LE line should be pulled HIGH. Changing attenuation state control values will change device state to new attenuation. Direct mode is ideal for manual control of the device (using hardwire, switches or jumpers). Serial Interface The Serial interface is an 8-bit Serial-In, Parallel-Out shift register buffered by a transparent latch. The 8- bits make up the Attenuation Word that controls the DSA. Figure 3 illustrates an example timing diagram for programming a state. The Serial interface is controlled using three CMOS- compatible signals: SI, Clock (CLK) and LE. The SI and CLK inputs allow data to be serially entered into the shift register. Serial data is clocked in LSB first. The shift register must be loaded while LE is held LOW to prevent the attenuator value from changing as data is entered. The LE input should then be toggled HIGH and brought LOW again, latching the new data into the DSA. The Attenuation Word truth table is listed in Table 5. A programming example of the serial register is illustrated in Figure 2. The Serial timing diagram is illustrated in Figure 3. It is required that all Parallel control inputs be grounded when the DSA is used in Serial mode. Power-up Control Settings The PE43711 will always initialize to the maximum attenuation setting (31.75 dB) on power-up for both the Serial and Latched Parallel modes of operation and will remain in this setting until the user latches in the next programming word. In Direct Parallel mode, the DSA can be preset to any state within the 31.75 dB range by pre-setting the Parallel control pins prior to power-up. In this mode, there is a 400 µs delay between the time the DSA is powered-up to the time the desired state is set. During this power-up delay, the device attenuates to the maximum attenu- ation setting (31.75 dB) before defaulting to the user defined state. If the control pins are left floating in this mode during power-up, the device will default to the minimum attenuation setting (insertion loss state). Dynamic operation between Serial and Parallel programming modes is possible. If the DSA powers up in Serial mode (P/S= HIGH), all the Parallel control inputs DI[6:0] must be set to logic LOW. Prior to toggling to Parallel mode, the DSA must be programmed serially to ensure D[7] is set to logic LOW. If the DSA powers up in either Latched or Direct Parallel mode, all Parallel pins DI[6:0] must be set to logic LOW prior to toggling to Serial mode (P/S= HIGH), and held LOW until the DSA has been programmed serially to ensure bit D[7] is set to logic LOW. The sequencing is only required once on power-up. Once completed, the DSA may be toggled between Serial and Parallel programming modes at will. |
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