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PE613010 Datasheet(PDF) 5 Page - Peregrine Semiconductor |
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PE613010 Datasheet(HTML) 5 Page - Peregrine Semiconductor |
5 / 8 page Page 5 of 8 DOC-11414-5 │ www.psemi.com ©2013–2014 Peregrine Semiconductor Corp. All rights reserved. Product Specification PE613010 Figure 5. Evaluation Board Evaluation Board The 101-0738 Evaluation Board (EVB) was designed for accurate measurement of the tuning switch impedance and loss using 2 Port Series (J4, J5) configuration. Three calibration standards are provided. The open (J2) and short (J1) standards (104 ps delay) are used for performing port extensions and accounting for electrical length and transmission line loss. The Thru (J8, J10) standard can be used to estimate PCB transmission line loss for scalar de-embedding. The board consists of a 4 layer stack with 2 outer layers made of Rogers 4350B (εr = 3.48) and 2 inner layers of FR4 (εr = 4.80). The total thickness of this board is 62 mils (1.57 mm). The inner layers provide a ground plane for the transmission lines. Each transmission line is designed using a coplanar waveguide with ground plane (CPWG) model using a trace width of 32 mils (0.813 mm), gap of 15 mils (0.381 mm), and a metal thickness of 1.4 mils (0.051 mm). PRT-08405 |
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