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BQ294704DSGT Datasheet(PDF) 10 Page - Texas Instruments |
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BQ294704DSGT Datasheet(HTML) 10 Page - Texas Instruments |
10 / 24 page 10 bq2947 SLUSB15E – SEPTEMBER 2012 – REVISED FEBRUARY 2016 www.ti.com Product Folder Links: bq2947 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Feature Description (continued) 8.3.1 Pin Details 8.3.1.1 Input Sense Voltage, Vx These inputs sense each battery cell voltage. A series resistor and a capacitor across the cell for each input is required for noise filtering and stable voltage monitoring. 8.3.1.2 Output Drive, OUT This terminal serves as the fault signal output, and may be ordered in either Active High or Open Drain Active Low options. 8.3.1.3 Supply Input, VDD This terminal is the unregulated input power source for the IC. A series resistor is connected to limit the current, and a capacitor is connected to ground for noise filtering. 8.3.1.4 External Delay Capacitor, CD This terminal is connected to an external capacitor that sets the delay timer during an overvoltage fault event. The CD pin includes a timeout detection circuit to ensure that the output drives active even with a shorted or open capacitor during an overvoltage event. The capacitor connected on the CD pin rapidly charges to a voltage if any one of the cell inputs exceeds the OV threshold. Then the delay circuit gradually discharges the capacitor on the CD pin. Once this capacitor discharges below a set voltage, the OUT transitions from an inactive to active state. To calculate the delay, use the following equation: tCD (sec) = K × CCD (µF), where K = 10 to 20 range. (1) Example: If CCD= 0.1 µF (typical), then the delay timer range is tCD (s) = 10 × 0.1 = 1 s (Minimum) tCD (s) = 20 × 0.1 = 2 s (Maximum) NOTE The tolerance on the capacitor used for CCD increases the range of the tCD timer. 8.4 Device Functional Modes 8.4.1 NORMAL Mode When all of the cell voltages are below the overvoltage threshold, VOV, the device operates in NORMAL mode. The device monitors the differential cell voltages connected across (V1–VSS), (V2–V1), (V3–V2), and (V4–V3). The OUT pin is inactive, and is low if configured active high, or, if configured active low, is an open drain being externally pulled up. 8.4.2 OVERVOLTAGE Mode OVERVOLTAGE mode is detected if any of the cell voltage exceeds the overvoltage threshold, VOV for configured OV delay time. The OUT pin is activated after a delay time set by the capacitance in the CD pin. The OUT pin will either pull high internally, if configured as active high, or will be pulled low internally if configured as active low. An external FET is then turned on, shorting the fuse to ground, which allows the battery and/or charger power to blow the fuse. When all of the cell voltages fall below the (VOV–VHYS), the device returns to NORMAL mode. 8.4.3 Customer Test Mode It is possible to reduce test time for checking the overvoltage function by simply shorting the external CD capacitor to VSS. In this case, the OV delay would be reduced to the t(CD_GND) value, which has a maximum of 170 ms. |
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