1 BOOT

2 VIN

3 PGND

4 PGND

5 PGND

AGND 12

VIN 11

PGND 10

PGND 9

PGND 8

BOTTOM VIEW

TOP VIEW

BOOT 1

VIN 2

PGND 3

PGND 4

PGND 5

12 AGND

11 VIN

10 PGND

9 PGND

8 PGND

7

6

SW

7

6

SW

3

TPS56C215

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SLVSD05A – MARCH 2016 – REVISED MARCH 2016

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5 Pin Configuration and Functions

RNN Package

18-Pin VQFN

Pin Functions

PIN

I/O

DESCRIPTION

NAME

NO.

BOOT

1

I

Supply input for the gate drive voltage of the high-side MOSFET. Connect a 0.1uF ceramic capacitor

between BOOT and SW.

VIN

2,11

P

Input voltage supply pin

PGND

3, 4, 5,

8, 9, 10

G

GND terminal for the controller circuit and the internal circuitry

SW

6, 7

O

Switch node

AGND

12

G

Ground of internal analog circuitry. Connect GND to PGND plane with a short trace.

FB

13

I

Converter feedback input. Connect to output voltage with resistor divider

SS

14

O

Connecting an external capacitor sets the SS time. If no external capacitor is connected the startup is with a

default of 1 ms

EN

15

I

Enable input control, floats high.

PGOOD

16

O

Open Drain Power Good Indicator, becomes low if output voltage is low due to thermal shutdown, OV, EN

shutdown or during SS.

VREG5

17

I/O

4.7-V LDO output that supplies internal circuitry and gate driver. Bypass it with a 4.7-µF capacitor. Can also

be driven externally with a 5V input

MODE

18

I

Connect this pin to a resistor divider between VREG5 and GND for different options