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LM3880MF-1AE Datasheet(PDF) 10 Page - Texas Instruments |
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LM3880MF-1AE Datasheet(HTML) 10 Page - Texas Instruments |
10 / 29 page GND VCC FLAG1 FLAG2 FLAG3 Sequence Control EN Timing Delay Generation Master Clock EPROM (Factory Set) + - 1.25V td1 td2 td3 td4 td5 td6 7 PA 10 LM3880, LM3880-Q1 SNVS451K – AUGUST 2006 – REVISED FEBRUARY 2016 www.ti.com Product Folder Links: LM3880 LM3880-Q1 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated 7 Detailed Description 7.1 Overview The LM3880 Simple Power Supply Sequencer provides a simple solution for sequencing multiple rails in a controlled manner. Six independent timers are integrated to control the timing sequence (power up and power down) of three open-drain output flags. These flags permit connection to either a shutdown or enable pin of linear regulators and switchers to control the operation of the power supplies. This allows design of a complete power system without concern for large inrush currents or latch-up conditions that can occur. The timing sequence of the LM3880 is controlled entirely by the enable (EN) pin. Upon power up, all the flags are held low until this precision enable is pulled high. When the EN pin is asserted, the power-up sequence starts. An internal counter delays the first flag (FLAG1) from rising until a fixed time period has expired. When the first flag is released, another timer will begin to delay the release of the second flag (FLAG2). This process repeats until all three flags have sequentially been released. The power-down sequence is the same as power-up sequence, but in reverse. When the EN pin is deasserted a timer will begin that delays the third flag (FLAG3) from pulling low. The second and first flag will then follow in a sequential manner after their appropriate delays. The three timers that are used to control the power-down scheme can also be individually programmed and are completely independent of the power-up timers. 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 Enable Pin Operation The timing sequence of the LM3880 is controlled by the assertion of the enable signal. The enable pin is designed with an internal comparator, referenced to a bandgap voltage (1.25 V), to provide a precision threshold. This allows a delayed timing to be externally set using a capacitor or to start the sequencing based on a certain event, such as a line voltage reaching 90% of nominal. For an additional delayed sequence from the rail powering VCC, simply attach a capacitor to the EN pin as shown in Figure 12. |
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