EN

FLAG1

FLAG2

FLAG3

6

LM3880, LM3880-Q1

SNVS451K – AUGUST 2006 – REVISED FEBRUARY 2016

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Copyright © 2006–2016, Texas Instruments Incorporated

(1)

Limits are 100% production tested at 25°. Limits over the operating temperature range are ensured through correlation using Statistical

Quality Control (SQC) methods. The limits are used to calculate TI's Average Outgoing Quality Level (AOQL).

(2)

Typical numbers are at 25°C and represent the most likely parametric norm.

6.6 Electrical Characteristics

PARAMETER

TEST CONDITIONS

UNIT

Operating Quiescent current

25

80

µA

OPEN-DRAIN FLAGS

FLAGx Leakage Current

1

20

nA

FLAGx Output Voltage Low

0.4

V

POWER-UP SEQUENCE

Timer delay 1 accuracy

All Other Timing Options

–15%

15%

2 ms Timing Option

–20%

20%

Timer delay 2 accuracy

All Other Timing Options

–15%

15%

2 ms Timing Option

–20%

20%

Timer delay 3 accuracy

All Other Timing Options

–15%

15%

2 ms Timing Option

–20%

20%

POWER-DOWN SEQUENCE

Timer delay 4 accuracy

All Other Timing Options

–15%

15%

2 ms Timing Option

–20%

20%

Timer delay 5 accuracy

All Other Timing Options

–15%

15%

2 ms Timing Option

–20%

20%

Timer delay 6 accuracy

All Other Timing Options

–15%

15%

2 ms Timing Option

–20%

20%

TIMING DELAY ERROR

Ratio of timing delays

For x = 1 or 4

95%

105%

For x = 1 or 4, 2 ms option

90%

110%

Ratio of timing delays

For x = 2 or 5

95%

105%

For x = 2 or 5, 2 ms option

90%

110%

ENABLE PIN

EN pin threshold

1.0

1.25

1.4

V

EN pin pullup current

7

µA

Timing Requirements

Sequence 1: All standard options use this sequence for output flags rise and fall order.

Figure 2. Power-Up Sequence