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LM3880QMF-1AA Datasheet(PDF) 11 Page - Texas Instruments |
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LM3880QMF-1AA Datasheet(HTML) 11 Page - Texas Instruments |
11 / 29 page EN FLAG1 td1 tenable_delay = 1.25V x CEN 7 PA 1.25V - + 7 PA Enable CEN EN 11 LM3880, LM3880-Q1 www.ti.com SNVS451K – AUGUST 2006 – REVISED FEBRUARY 2016 Product Folder Links: LM3880 LM3880-Q1 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Feature Description (continued) Figure 12. Capacitor Timing Using the internal pullup current source to charge the external capacitor (CEN) the enable pin delay can be calculated by Equation 1: (1) A resistor divider can also be used to enable the LM3880 based on a certain voltage threshold. Take care when sizing the resistor divider to include the effects of the internal current source. One of the features of the EN pin is that it provides glitch free operation. The first timer will start counting at a rising threshold, but will always reset if the EN pin is deasserted before the first output flag is released. This can be shown in Figure 13: Figure 13. EN Glitch 7.3.2 Incomplete Sequence Operation If the enable signal remains high for the entire power-up sequence, then the part will operate as shown in the standard timing diagrams. However, if the enable signal is de-asserted before the power-up sequence is completed the part will enter a controlled shutdown. This allows the system to walk through a controlled power cycling, preventing any latch conditions from occurring. This state only occurs if the enable pin is deasserted after the completion of timer 1, but before the entire power-up sequence is completed. When this event occurs, the falling edge of EN pin resets the current timer and will allow the remaining power-up cycle to complete before beginning the power-down sequence. The power down sequence starts approximately 120 ms after the final power-up flag. This allows output voltages in the system to stabilize before everything is shut down. An example of this operation can be seen in Figure 14: |
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