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LM5066 Datasheet(PDF) 11 Page - Texas Instruments |
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LM5066 Datasheet(HTML) 11 Page - Texas Instruments |
11 / 65 page 11 LM5066 www.ti.com SNVS655I – JUNE 2011 – REVISED JANUARY 2016 Product Folder Links: LM5066 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated 7.7 Switching Characteristics Unless otherwise stated, the following conditions apply: VVIN = 48 V, –40°C < TJ < 125°C, VUVLO = 3 V , VOVLO = 0 V, RPWR= 20 k Ω. PARAMETER CONDITIONS MIN TYP MAX UNIT UVLO/EN, OVLO PINS UVLODEL UVLO delay Delay to GATE high 9 µs Delay to GATE low 13 OVLODEL OVLO delay Delay to GATE high 13 µs Delay to GATE low 10 FB PIN FBDEL FB Delay Delay to PGD high 7.6 µs Delay to PGD low 9.2 CURRENT LIMIT tCL Response time VIN-SENSE stepped from 0 to 80 mV; CL = GND 45 µs CIRCUIT BREAKER tCB Response time VIN-SENSE stepped from 0 to 150 mV, time to GATE low, no load 0.42 0.83 µs TIMER (TIMER PIN) tFAULT_DELAY Fault to GATE low delay TIMER pin reaches the upper threshold 12 µs |
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