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LMG5200MOFT Datasheet(PDF) 5 Page - Texas Instruments |
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LMG5200MOFT Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 23 page  LMG5200 www.ti.com SNOSCY4B – MARCH 2015 – REVISED JANUARY 2016 6.5 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENTS IVCC VCC quiescent current LI = HI = 0 V, VVCC = 5 V 0.07 0.1 mA ICCO VCC operating current f = 500 kHz 3.0 5.0 mA IHB Total HB quiescent current LI = HI = 0 V, VVCC = 5 V 0.09 0.120 mA f = 500 kHz, 50% Duty cycle, IHBO Total HB operating current 1.5 2 mA VDD = 5 V INPUT PINS VIH High-level input voltage Rising edge 1.89 2.06 2.18 V VIL Low-level input voltage Falling edge 1.48 1.66 1.76 V Hysteresis between rising and falling VHYS 400 mV threshold RI Input pull-down resistance 100 200 300 k Ω UNDERVOLTAGE PROTECTION VVCC VCC rising edge threshold Rising 3.2 3.8 4.5 V Hysteresis between falling and rising VVCC(hyst) 185 mV edge VHB HB rising edge threshold Rising 2.7 3.2 3.7 V HB hysteresis between rising edge 185 mV and falling edge BOOTSTRAP DIODE VDL Low-current forward voltage IVDD-HB = 100 µA 0.45 0.65 V VDH High-current forward voltage IVDD-HB = 100 mA 0.9 1.0 V RD Dynamic resistance 1.6 2.8 Ω HB-HS clamp Regulation voltage 4.7 5 5.3 V Bootstrap diode reverse recovery tBS IF = 100 mA, IR = 100 mA 40 ns time Bootstrap diode reverse recovery QRR VVIN = 50 V 2 nC charge POWER STAGE RDS(on)HS High-side GaN FET on-resistance IOUT = 5 A, VVCC = 5 V, TJ = 25ºC 14 18 m Ω RDS(on)LS Low-side GaN FET on-resistance IOUT = 5 A, VVCC = 5 V, TJ = 25ºC 14 18 m Ω ISD = 500 mA, VIN floating, VSD GaN 3rd quadrant conduction drop 2 V VVCC = 5 V, HI, LI low Leakage between VIN to SW when VIN = 80 V, (HI = LI = 0 V) IL-VIN-SW the high-side GaN FET and low-side 25 150 µA VVCC = 5 V, TJ = 25ºC GaN FET are off Leakage between SW and GND VSW = 80 V, HI , LI = 0 V, VVCC = 5 IL-SW-GND when the high-side GaN FET and V, 25 150 µA low-side GaN FET are off TJ = 25ºC Output capacitance of high-side VDS = 50 V, VGS = 0 V COSS 225 280 pF GaN FET and low-side GaN FET (HI = LI = 0 V) QG Total gate charge VDS = 50 V, ID = 10 A, VGS = 5 V 3.8 nC QOSS Output charge VDS = 50 V, ID = 10 A 20 nC Source to drain reverse recovery Not including internal driver QRR 0 nC charge bootstrap diode Copyright © 2015–2016, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LMG5200 |
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