Thermal Pad

(Bottom Side)

21

GND

EN

RT

SYNC

VIN

PVIN

PVIN

PGND

PGND

PGND

PH

PH

PH

PH

PH

BOOT

VSENSE

COMP

SS/TR

PWRGD

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

TPS50301-HT

SLVSA94I – DECEMBER 2012 – REVISED JANUARY 2016

www.ti.com

5 Description (continued)

The output voltage startup ramp is controlled by the SS/TR pin which allows operation as either a stand alone

power supply or in tracking situations. Power sequencing is also possible by correctly configuring the enable and

the open drain power good pins.

Cycle-by-cycle current limiting on the high-side FET protects the device in overload situations and is enhanced

by a low-side sourcing current limit which prevents current runaway. There is also a low-side sinking current limit

which turns off the low-side MOSFET to prevent excessive reverse current. Thermal shutdown disables the part

when die temperature exceeds thermal shutdown temperature.

6 Pin Configuration and Functions

HKH Package

20-Pin CFP

Bottom View

Pin Functions

PIN

DESCRIPTION

NO.

NAME

1

GND

EN pin has an internal pullup thus EN pin can be floated to enable the device. As an option external pullup can also

2

EN

be added if desired. Adjust the input undervoltage lockout (UVLO) with two resistors.

3

RT

In internal oscillation mode, a resistor is connected between the RT pin and GND to set the switching frequency.

4

SYNC

Optional 1-MHz external system clock input. The device operates with an internal oscillator if this pin is left open.

5

VIN

Supplies the power to the output FET controllers

6

PVIN

Power input. Supplies the power switches of the power converter

7

8

9

PGND

Return for low-side power MOSFET

10

(1)

Thermal pad (analog ground) must be connected to PGND external to the package.

4

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