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TPS65020RHARG4 Datasheet(PDF) 5 Page - Texas Instruments |
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TPS65020RHARG4 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 53 page  TPS65020 www.ti.com SLVS607D – SEPTEMBER 2005 – REVISED JANUARY 2016 Pin Functions (continued) PIN I/O DESCRIPTION NAME NO. PGND2 34 Power ground for VDCDC2 converter PGND3 3 Power ground for VDCDC3 converter PowerPAD™ – Connect the power pad to analog ground Power supply for digital and analog circuitry of VDCDC1, VDCDC2, and VDCDC3 DC-DC converters. VCC 37 I This must be connected to the same voltage supply as VINDCDC3, VINDCDC1, and VINDCDC2. Also supplies serial interface block VDCDC1 9 I VDCDC1 feedback voltage sense input, connect directly to VDCDC1 VDCDC2 33 I VDCDC2 feedback voltage sense input, connect directly to VDCDC2 VDCDC3 2 I VDCDC3 feedback voltage sense input, connect directly to VDCDC3 Input voltage for VDCDC1 step-down converter. This must be connected to the same voltage supply VINDCDC1 6 I as VINDCDC2, VINDCDC3, and VCC. Input voltage for VDCDC2 step-down converter. This must be connected to the same voltage supply VINDCDC2 36 I as VINDCDC1, VINDCDC3, and VCC. Input voltage for VDCDC3 step-down converter. This must be connected to the same voltage supply VINDCDC3 5 I as VINDCDC1, VINDCDC2, and VCC. LDO REGULATOR SECTION LDO_EN 22 I Enable input for LDO1 and LDO2. Logic high enables the LDOs, logic low disables the LDOs VBACKUP 15 I Connect the backup battery to this input pin. VINLDO 19 I I Input voltage for LDO1 and LDO2 VLDO1 20 O Output voltage of LDO1 VLDO2 18 O Output voltage of LDO2 VRTC 16 O Output voltage of the LDO and switch for the real time clock VSYSIN 14 I Input of system voltage for VRTC switch CONTROL AND I2C SECTION HOT_RESET 11 I Push button input used to reboot or wake-up processor through the RESPWRON output pin INT 28 O Open-drain output LOW_BAT 21 O Open-drain output of LOW_BAT comparator LOWBAT_SNS 39 I Input for the comparator driving the LOW_BAT output PB_IN 12 I/O Push button input debounced and output fed to latch at PB_OUT PB_OUT 13 I/O Open-drain output of latch driven by PB_IN. Low after power up. PWRFAIL 31 O Open-drain output. Active-low when PWRFAIL comparator indicates low VBAT condition. PWRFAIL_SNS 38 I Input for the comparator driving the PWRFAIL output RESPWRON 27 O Open-drain System reset output SCLK 30 I Serial interface clock line SDAT 29 I/O Serial interface data and address TRESPWRON 26 I Connect the timing capacitor to this pin to set the reset delay time: 1 nF → 100 ms Copyright © 2005–2016, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: TPS65020 |
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