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SP690S Datasheet(PDF) 6 Page - Sipex Corporation |
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SP690S Datasheet(HTML) 6 Page - Sipex Corporation |
6 / 20 page SP690T/S/R DS/10 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory © Copyright 2000 Sipex Corporation 6 PIN ASSIGNMENTS Pin 1 —V OUT — Output Supply Voltage for CMOS RAM. When V CC is above the reset threshold, V OUT connects to VCC through a P-channel MOSFET switch. When V CC falls below the VSW and V BATTERY, VBATTERY connects to VOUT. Connect to V CC if no battery is used. Pin 2 — V CC — +5V Supply Input Pin 3 — GND — Ground reference for all signals Pin 4 — PFI — Power-Fail Comparator Input. When PFI is less than 1.25V or when V CC falls below the V SW, PFO goes LOW, otherwise PFO remains HIGH. Connect to GND if unused. Pin 5 — PFO — Power-Fail Comparator Output. Leave open if unused. Pin 6 — WDI — Watchdog Input. If WDI remains HIGH or LOW for 1.6 seconds, the internal watchdog timer triggers a reset. The internal watchdog timer clears when reset is asserted or WDI sees a rising or falling edge. The watchdog function cannot be disabled. Pin 7 for SP690_/802_ only — Active-LOW Reset Output. — Whenever RESET is triggered by a watchdog timeout, it goes LOW for 200ms. It stays LOW whenever V CC is below the reset threshold and re- mains LOW for 200ms after V CC rises above the reset threshold or when the watchdog triggers a reset. Pin 7 for SP804_/805_ only — Active-HIGH Open-Drain Reset Output. — The inverse operation of RESET. Pin 8 — V BATTERY — Backup-Battery Input. When V CC falls below VSW and VBATTERY, V OUT switchesfrom VCC to VBATTERY. When V CC rises above the reset threshold, V OUT reconnects to VCC. VBATTERY may exceed V CC. Connect to VCC if no battery is used. VOUT VCC GND PFI VBATTERY RESET / RESET* WDI PFO 1 2 3 4 5 6 7 8 *SP804T/S/R and SP805T/S/R only SP690T/S/R SP802T/S/R SP804T/S/R SP805T/S/R PINOUT |
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