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BQ33100PW Datasheet(PDF) 3 Page - Texas Instruments |
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BQ33100PW Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 67 page  1 2 3 NC 4 VCCPACK 5 6 VC2 7 VC3 8 VC4 9 10 SRP CHG VCC NC 24 CHGOR 23 REG 27 22 GND 21 VC1 SRN TS VC5 RBI 20 19 LLEN 18 SCL 17 16 15 FAULT 11 12 CHGLVL0 SDA 14 13 VC5BAL CHGLVL1 3 bq33100 www.ti.com SLUS987B – JANUARY 2011 – REVISED DECEMBER 2015 Product Folder Links: bq33100 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated (1) I = Input, O = Output, P = Power, IA = Analog Input, OD = Open Drain 5 Description (Continued) Using its integrated high-performance analog peripherals, the bq33100 measures and maintains an accurate record of available capacitance, state-of-health, voltage, current, temperature, and other critical parameters in Super Capacitors, and reports the information to the system host controller over a 2-wire SMBus 1.1 compatible interface. The bq33100 provides firmware controlled protection on overvoltage, overtemperature, and overcharge along with hardware controlled protection for overcurrent in discharge and short circuit protection during charge and discharge. 6 Pin Configuration and Functions PW Package 24-Pin TSSOP Top View Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. CHG 23 O P-Channel FET drive for controlling charge CHGLVL0 11 O Charge Control Output 0 CHGLVL1 12 O Charge Control Output 1 CHGOR 21 I CHG Over Ride input. If not used connect to VSS FAULT 15 O Active high output to indicate fault condition. GND 19 P Ground LLEN 17 O Learn Load Enable Output NC 2 O Not used and must be connected to VCC NC 22 - No connect, leave pin floating RBI 18 P RAM backup pin to provide backup potential to the internal DATA RAM if power is momentarily lost by using a capacitor attached between RBI and GND REG27 20 P Internal power supply 2.7-V bias output SCL 16 I/OD Serial clock input: Clocks data on SDA SDA 14 I/OD Serial Data: Transmits and Receives data SRN 8 IA Analog input pin connected to the internal ADC peripheral for measuring a small voltage between SRP and SRN where SRN is the bottom of the sense resistor. SRP 7 IA Analog input pin connected to the internal ADC peripheral for measuring a small voltage between SRP and SRN where SRP is the top of the sense resistor. TS 9 IA Thermistor input VC1 3 IA Sense voltage input terminal and external capacitor voltage balancing drive output for the 5th series capacitor, and stack measurement input. See Series Capacitor Configuration for systems with less than 5 series VC2 4 IA Sense voltage input terminal and external capacitor voltage balancing drive output for the 4th series capacitor. See Series Capacitor Configuration for systems with less than 5 series |
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