TLC59108F

SLDS162B – MARCH 2009 – REVISED DECEMBER 2015

www.ti.com

6.6 I

STANDARD-MODE

FAST-MODE

FAST-MODE PLUS

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

SCL clock frequency

0

100

0

400

0

1000

kHz

4.7

1.3

0.5

μs

Start

Hold time (repeated) for Start

4

0.6

0.26

μs

condition

Set-up time (repeated) for Start

4.7

0.6

0.26

μs

condition

Set-up time for Stop condition

4

0.6

0.26

μs

Data hold time

0

0

0

ns

0.3

3.45

0.1

0.9

0.05

0.45

μs

0.3

3.45

0.1

0.9

0.05

0.45

μs

Data set-up time

250

100

50

ns

Low period of the SCL clock

4.7

1.3

0.5

μs

High period of the SCL clock

4

0.6

0.26

μs

Fall time of both SDA and SCL

20 +

300

300

120

ns

(5)

Rise time of both SDA and SCL

20 +

1000

300

120

ns

signals

(5)

Pulse width of spikes that must be

50

50

50

ns

Reset

Reset pulse width

10

10

10

ns

Reset recovery time

0

0

0

ns

400

400

400

ns

(1)

(2)

(3)

bridge the undefined region of SCLs falling edge.

(4)

at 250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines

(5)

(6)

Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns

(7)

Resetting the device while actively communicating on the bus may cause glitches or errant Stop conditions.

(8)

6

Submit Documentation Feedback

Copyright © 2009–2015, Texas Instruments Incorporated

Product Folder Links: TLC59108F