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TPS65265RHBT Datasheet(PDF) 4 Page - Texas Instruments |
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TPS65265RHBT Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 47 page  TPS65265 SLVSD86A – DECEMBER 2015 – REVISED DECEMBER 2015 www.ti.com Pin Functions PIN DESCRIPTION NO. NAME 1 V7V Internal LDO for gate driver and internal controller. Connect a 1 µF capacitor from the pin to power ground An open drain output, asserts low if output voltage of any buck beyond regulation range due to thermal 2 PGOOD shutdown, over-current, under-voltage or ENx shut down. Enable for buck1. Float to enable. Can use this pin to adjust the input undervoltage lockout (UVLO) of buck1 3 EN1 with a resistor divider. 4 EN2 Enable for buck2. Float to enable. Can use this pin to adjust the input UVLO of buck2 with a resistor divider. 5 EN3 Enable for buck3. Float to enable. Can use this pin to adjust the input UVLO of buck3 with a resistor divider. 6 FB2 Feedback Kelvin sensing pin for buck2 output voltage. Connect this pin to buck2 resistor divider. Error amplifier output and Loop compensation pin for buck2. Connect a series resistor and capacitor to 7 COMP2 compensate the control loop of buck2 with peak current PWM mode. When floating, Buck1/2/3 are controlled separate by EN1/2/3. When tied to HIGH or tied to GND, an automatic 8 MODE power-up/power-down sequence is provided according to states of EN1, EN2 and EN3 pins. Boot strapped supply to the high side floating gate driver in buck2. Connect a capacitor (recommend 47nF) 9 BST2 from BST2 pin to LX2 pin. Power ground connection of buck2. Connect PGND2 pin as close as practical to the (-) terminal of PVIN2 input 10 PGND2 ceramic capacitor. Switching node connection to the inductor and bootstrap capacitor for buck2. The voltage swing at this pin is 11 LX2 from a diode voltage below the ground up to PVIN2 voltage. Input power supply for buck2. Connect PVIN2 pin as close as practical to the (+) terminal of an input ceramic 12 PVIN2 capacitor (suggest 10 µF). Input power supply for buck3. Connect PVIN3 pin as close as practical to the (+) terminal of an input ceramic 13 PVIN3 capacitor (suggest 10 µF). Switching node connection to the inductor and bootstrap capacitor for buck3. The voltage swing at this pin is 14 LX3 from a diode voltage below the ground up to PVIN3 voltage. Power ground connection of buck3. Connect PGND3 pin as close as practical to the (-) terminal of PVIN3 input 15 PGND3 ceramic capacitor. Boot strapped supply to the high side floating gate driver in buck3. Connect a capacitor (recommend 47nF) 16 BST3 from BST3 pin to LX3 pin. Delay time programmable between bucks at automatic power sequencing mode. Connect an external capacitor 17 SEQ_DLY to set the interval delay time. Error amplifier output and Loop compensation pin for buck3. Connect a series resistor and capacitor to 18 COMP3 compensate the control loop of buck3 with peak current PWM mode. 19 FB3 Feedback Kelvin sensing pin for buck3 output voltage. Connect this pin to buck3 resistor divider. 20 ROSC Oscillator frequency programmable pin. Connect an external resistor to set the switching frequency. 21 AGND Analog ground common to buck controllers and other analog circuits. 22 FB1 Feedback Kelvin sensing pin for buck1 output voltage. Connect this pin to buck1 resistor divider. Error amplifier output and Loop compensation pin for buck1. Connect a series resistor and capacitor to 23 COMP1 compensate the control loop of buck1 with peak current PWM mode. 24 PG_DLY PGOOD delay programmable pin. Connect an external capacitor to set the delay time. Boot strapped supply to the high side floating gate driver in buck1. Connect a capacitor (recommend 47nF) 25 BST1 from BST1 pin to LX1 pin. Power ground connection of Buck1. Connect PGND1 pin as close as practical to the (-) terminal of PVIN1 input 26, 27 PGND1 ceramic capacitor. Switching node connection to the inductor and bootstrap capacitor for buck1. The voltage swing at this pin is 28, 29 LX1 from a diode voltage below the ground up to PVIN1 voltage. Input power supply for buck1. Connect PVIN1 pin as close as practical to the (+) terminal of an input ceramic 30, 31 PVIN1 capacitor (suggest 22 µF). 32 PSM Ties to HIGH or leaves floating, PSM mode; Ties to GND, FCCM mode. There is no electric signal down bonded to thermal pad inside IC. Exposed thermal pad must be soldered to PAD PCB for optimal thermal performance. 4 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65265 |
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