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TPS92691-Q1 Datasheet(PDF) 6 Page - Texas Instruments |
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TPS92691-Q1 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 46 page  TPS92691, TPS92691-Q1 SLVSD68 – DECEMBER 2015 www.ti.com Electrical Characteristics (continued) TJ = –40°C to 140°C, VIN = 14 V, VIADJ = 2.2 V, CVCC = 1 µF, CCOMP = 2.2 nF, RCS = 100 mΩ, RT = 20 kΩ, VPWM = 5 V, no load on GATE and DDRV (unless otherwise noted) (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT D = DMAX (with max slope ILV + ISL IS level shift source current 115 µA compensation) CURRENT SENSE AMPLIFIER (CSP, CSN) Cumulative offset voltage at VCSP = 60 –40°C ≤ TJ ≤ 140°C –5.2 5.9 mV V and V(CSP-CSN) = 150 mV, referred to 25°C ≤ TJ ≤ 140°C –4.4 4.6 mV current sense input Cumulative offset voltage at VCSP = 60 –40°C ≤ TJ ≤ 140°C –3.5 5.0 mV V and V(CSP-CSN) = 10 mV, referred to 25°C ≤ TJ ≤ 140°C -2.8 4.0 mV current sense input VCS(offset) Cumulative offset voltage at VCSN = 0 –40°C ≤ TJ ≤ 140°C –5.9 6.7 mV V and V(CSP-CSN) = 150 mV, referred to 25°C ≤ TJ ≤ 140°C -4.7 5.0 mV current sense input Cumulative offset voltage at VCSN = 0 –40°C ≤ TJ ≤ 140°C –2.3 3.2 mV V and V(CSP-CSN) = 10 mV, referred to 25°C ≤ TJ ≤ 140°C –1.7 2.6 mV current sense input CS(BW) Current sense unity gain bandwidth 500 kHz ICS(BIAS) CSP, CSN bias current VCSP, CSN = 60 V 4 µA CURRENT MONITOR (IMON) VIMON(CLP) IMON output voltage clamp 3.2 3.7 4.2 V VIMON(OS) IMON buffer offset voltage –11.4 –1.6 7.3 mV ANALOG ADJUST (IADJ) VIADJ(CLP) IADJ internal clamp voltage IIADJ = 1 µA 2.27 2.42 2.55 V IIADJ(BIAS) IADJ input bias current VIADJ < 2.2 V 90 nA RIADJ(LMT) IADJ current limiting series resistor VIADJ > 2.6 V 12 k Ω ERROR AMPLIFIER (COMP) gM Transconductance 121 µA/V ICOMP(SRC) COMP current source capacity VIADJ = 1.4 V, V(CSP-CSN) = 0 V 130 µA ICOMP(SINK) COMP current sink capacity VIADJ = 0 V, V(CSP-CSN) = 0.1 V 130 µA EA(BW) Error amplifier bandwidth –3 dB 5 MHz VCOMP(RST) COMP pin reset voltage 100 mV RCOMP(DCH) COMP discharge FET resistance 246 Ω SOFT-START (SS) ISS Soft-start source current 7 10 12.8 µA VSS(RST) Soft-start pin reset voltage 25 mV RSS(DCH) SS discharge FET resistance 260 Ω OVERVOLTAGE PROTECTION (OVP) VOVP(THR) OVP detection threshold 1.18 1.24 1.31 V IOVP(HYS) OVP hysteresis current 12 20 27.5 µA PWM INPUT (PWM) Schmitt trigger logic level (high VPWM(HIGH) 2.5 2.7 V threshold) Schmitt trigger logic level (low VPWM(LOW) 2.0 2.3 V threshold) RPWM(PD) PWM pulldown resistance 1 M Ω tDLY(RISE) PWM to DDRV rising delay 54 ns tDLY(FALL) PWM to DDRV falling delay 72 ns PWM GATE DRIVE OUTPUT (DDRV) RDH DDRV high-side resistance 6.1 12.8 Ω RDL DDRV low-side resistance 5.2 11.4 Ω 6 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS92691 TPS92691-Q1 |
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