TPS2559-Q1

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SLVSD03 – DECEMBER 2015

Feature Description (continued)

9.3.2 Overcurrent Protection

The TPS2559-Q1 responds to overcurrent conditions by limiting their output current to IOS. When an overload

The first condition is when a short circuit or partial short circuit is present when the device is powered-up or

enabled. The output voltage is held near zero potential with respect to ground and the TPS2559-Q1 ramps the

device begins to thermal cycle (see Figure 24).

The second condition is when a short circuit, partial short circuit, or transient overload occurs while the device is

response speed and shape will vary with the overload level, input circuit, and rate of application. The current-limit

thermal cycle.

The TPS2559-Q1 thermal cycles if an overload condition is present long enough to activate thermal limiting in

any of the above cases. The device turns off when the junction temperature exceeds 135°C (min) while in current

limit. The device remains off until the junction temperature cools 20°C (typ) and then restarts. The TPS2559-Q1

cycles on/off until the overload is removed (see Figure 25).

9.3.3 FAULT Response

The FAULT open-drain output is asserted (active low) during an over-current or over-temperature condition. The

TPS2559-Q1 asserts the FAULT signal until the fault condition is removed and the device resumes normal

operation. The TPS2559-Q1 is designed to eliminate false FAULT reporting by using an internal delay "deglitch"

circuit for over-current (9-ms typ.) conditions without the need for external circuitry. This ensures that FAULT is

not accidentally asserted due to normal operation such as starting into a heavy capacitive load. The deglitch

circuitry delays entering and leaving current-limit induced fault conditions. The FAULT signal is not deglitched

when the MOSFET is disabled due to an over-temperature condition but is deglitched after the device has cooled

and begins to turn on. This unidirectional deglitch prevents FAULT oscillation during an over-temperature event.

9.4 Device Functional Modes

The undervoltage lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO turn-

on threshold. Built-in hysteresis prevents unwanted on/off cycling due to input voltage droop during turn on.

9.4.2 Operation with EN Control

The logic enable controls the power switch and device supply current. The supply current is reduced to less than

2-

μA when a logic low is present on EN. A logic high input on EN enables the driver, control circuits, and power

switch. The enable input is compatible with both TTL and CMOS logic levels.

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