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PI6C59S6005ZDIE Datasheet(PDF) 9 Page - Pericom Semiconductor Corporation |
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PI6C59S6005ZDIE Datasheet(HTML) 9 Page - Pericom Semiconductor Corporation |
9 / 13 page 9 PI6C59S6005 Rev B 10/27/2014 PI6C59S6005 6 GHz Selectable Fanout Buffer with Internal Termination LVPECL and LVDS Input Interface LVPECL and LVDS DC Input LVPECL and LVDS clock input to this IC is connected as shown in the Fig. 3. LVPECL and LVDS AC Input LVPECL and LVDS AC drive to this clock IC requires the use of the VREF-AC output to recover the DC bias for the IC input as shown in Fig. 4 CML AC-Coupled Input CML AC-coupled drive requires a connection to VREF-AC as shown in Fig. 5. The CML DC drive is not recommended as different vendors have different CML DC voltage level. CML is mostly used in AC coupled drive configuration for data and clock signals. Fig 3: LVPECL/ LVDS Input Fig 4: LVPECL/ LVDS AC Coupled Input Fig 5: CML AC-Coupled Input Interface HCSL AC-Coupled Input It is suggested to use AC coupling to buffer PCIe HCSL 100MHz clock since its V_cm is relatively low at about 0.4V, as shown in Fig. 6. CMOS Clock DC Drive Input LVCMOS clock has voltage Voh levels such as 3.3V, 2.5V, 1.8V. CMOS drive requires a Vcm design at the input: Vcm= ½ (CMOS V) as shown in Fig. 7. Rs =22 ~33ohm typically. Fig 6: HCSL AC-Coupled Input Interface Fig 7: CMOS DC Input Vcm Design Device IC + - Zo =100 *150 *150 LVPECL Drive REF_IN+ REF_IN- VTH VREF-AC 50 50 *150 removed for LVDS Device IC + - Zo =100 REF_IN+ REF_IN- VTH VREF-AC 50 50 VDD 0.01uf 0.01u 0.01u LVPECL Drive *150 *150 *150 removed for LVDS Device IC + - Zo =100 CML REF_IN+ REF_IN- VTH VREF-AC 50 50 CML AC-Coupled VDD 0.01uf 0.01u 0.01u Device IC + - Zo =100 REF_IN+ REF_IN- VTH VREF-AC 50 50 VDD 0.01uf 0.01u 0.01u 33 33 HCSL PCIe Ref_CLK 50 50 CMOS Driver 3.3V, 2.5V, 1.8V Rs Zo Ro REF_IN+ REF_IN- VDD 3.3V 0.1u Rup Rdn Vcm design Vcm CMOS V Rup Rdn Vcm 3.3V 1k 1k 1.65V 2.5V 1k 610 1.25V 1.8V 1k 380 0.9V Diff. Input VTH VREF-AC 14-0182 |
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