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PI6C20800BAE Datasheet(PDF) 2 Page - Pericom Semiconductor Corporation |
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PI6C20800BAE Datasheet(HTML) 2 Page - Pericom Semiconductor Corporation |
2 / 10 page 2 www.pericom.com P-0.1 04/27/11 PI6C20800B PCI Express® 3.0 1:8 HCSL Clock Buffer Serial Data Interface (SMBus) PI6C20800B is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit address and read/write bit as shown below. Address assignment A6 A5 A4 A3 A2 A1 A0 R/W 1 1 0 1 1 1 0 0/1 Data Write Protocol(1) 1 bit 7 bits 1 1 8 bits 1 8 bits 1 8 bits 1 8 bits 1 1 bit Start bit Slave Addr W Ack Register offset Ack Byte Count = N Ack Data Byte Offset Ack Data Byte N - 1 Ack Stop bit Pinout Table Pin Name Type Pin # Descriptions SRC_DIV# Input 1 3.3V LVTTL input for selecting input frequency divide by 2, active LOW. SRC & SRC# Input 4, 5 0.7V Differential SRC input from PI6C410 clock synthesizer OE [0:7] Input 6, 7, 14, 15, 35, 36, 43, 44 3.3V LVTTL input for enabling outputs, active HIGH. OE_INV Input 40 3.3V LVTTL input for inverting the OE, SRC_STOP# and PWRDWN# pins. When 0 = same stage When 1 = OE[0:7], SRC_STOP#, PWRDWN# inverted. OUT[0:7] & OUT[0:7]# Output 8, 9, 12, 13, 16 17, 20, 21, 29, 30, 33, 34, 37, 38, 41, 42 0.7V Differential outputs PLL/BYPASS# Input 22 3.3V LVTTL input for selecting fan-out of PLL operation. SCLK Input 23 SMBus compatible SCLOCK input SDA I/O 24 SMBus compatible SDATA I REF Input 46 External resistor connection to set the differential output current SRC_STOP# Input 27 3.3V LVTTL input for SRC stop, active LOW PLL_BW# Input 28 3.3V LVTTL input for selecting the PLL bandwidth PWRDWN# Input 26 3.3V LVTTL input for Power Down operation, active LOW LOCK Output 45 3.3V LVTTL output, transition high when PLL lock is achieved (Latched output) V DD Power 2, 11, 19, 31, 39 3.3V Power Supply for Outputs V SS Ground 3, 10, 18, 25, 32 Ground for Outputs V SS_A Ground 47 Ground for PLL V DD_A Power 48 3.3V Power Supply for PLL Note: 1. Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0. 11-0049 |
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