TPS7B7701-Q1 datasheet(6/28 Pages) TI1

Part #	TPS7B7701-Q1

Description	Single- and Dual-Channel Antenna LDO

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Manufacturer	TI1 [Texas Instruments]

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TPS7B7701-Q1, TPS7B7702-Q1

SLVSCE8B – JANUARY 2015 – REVISED NOVEMBER 2015

www.ti.com

6.4 Thermal Information

TPS7B7701-Q1

TPS7B7702-Q1

THERMAL METRIC(1)

PWP (HTSSOP)

UNIT

16 PINS

RθJA

Junction-to-ambient thermal resistance(2)

45.9

40.3

°C/W

RθJC(top)

Junction-to-case (top) thermal resistance

29.2

27.7

°C/W

RθJB

Junction-to-board thermal resistance

24.7

22.3

°C/W

ψJT

Junction-to-top characterization parameter

1.3

0.8

°C/W

ψJB

Junction-to-board characterization parameter

24.5

22

°C/W

RθJC(bot)

Junction-to-case (bottom) thermal resistance

3.7

2.7

°C/W

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

(2)

The thermal data is based on JEDEC standard high K profile – JESD 51-7. The copper pad is soldered to the thermal land pattern. Also

correct attachment procedure must be incorporated

6.5 Electrical Characteristics

VI = 14 V, TJ = –40ºC to +150ºC, unless otherwise stated

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY VOLTAGE AND CURRENT (IN)

VI

Input voltage

4.5

40

V

TPS7B7701-Q1: VI = 4.5 to 40 V, V(EN) ≥ 2 V,

0.6

1

I(OUT) = 0.1 mA

IQ

Quiescent current

mA

TPS7B7702-Q1: VI = 4.5 to 40 V, V(EN1) and

0.6

1

V(EN2) ≥ 2 V, I(OUT1) and I(OUT2) = 0.1 mA

TPS7B7701-Q1: EN = GND

5

I(shutdown)

Shutdown current

µA

TPS7B7702-Q1: EN1 = EN2 = GND

5

TPS7B7701-Q1: V(EN) ≥ 2 V, I(OUT) ≤ 300 mA,

4.5

GND current

Inom

Operating current

mA

TPS7B7702-Q1: V(EN1) and V(EN2) ≥ 2 V, I(OUT1)

6

and I(OUT2) ≤ 300 mA, GND current

V(BG)

Bandgap

Reference voltage for FB

–2%

1.233

2%

V

V(UVLO)

Undervoltage lockout falling

Ramp IN down until the output turns off

4

V

Vhys

Hysteresis

0.4

V

INPUT CONTROL PINS (EN, EN1, EN2, SENSE_EN, AND SENSE_SEL)

For EN, EN1, EN2, SENSE_EN, and

VIL

Logic input low level

0

0.7

V

SENSE_SEL

For EN, EN1, EN2, SENSE_EN, and

VIH

Logic input high level

2

V

SENSE_SEL

II(SENSE_EN)

SENSE_EN input current

V(SENSE_EN) = 5 V, V(ENx) ≥ 2 V

10

µA

II(SENSE_SEL)

SENSE_SEL input current

V(SENSE_EN) = 5 V, V(ENx) ≥ 2 V

10

µA

II(EN)

Enable input current

V(ENx) ≤ 40 V

10

µA

REGULATED OUTPUT (OUT, OUT1, AND OUT2)

40 V

≥ VI ≥ VO + 1.5 V and VI ≥ 4.5 V, IO = 1 to

VO

Regulated output

–2%

2%

300 mA(1)

VI = VO + 1.5 V to 40 V and VI ≥ 6 V, IO = 10

ΔVO(ΔVI)

Line regulation

10

mV

mA, voltage variation on FB pin

IO = 1 mA to 200 mA, voltage variation on FB

ΔVO(ΔIO)

Load regulation

20

mV

V(DROPOUT)

Dropout voltage

Measured between IN and OUTx, IO = 100 mA

500

mV

IO

Output current

VO in regulation

0

300

mA

PSRR

Power supply ripple rejection(2)

IO = 100 mA, CO = 2.2 µF, ƒ = 100 Hz

73

dB

CURRENT SENSE AND CURRENT-LIMIT

IO/ISENSE

OUTx to SENSEx current ratio (IO / ISENSEx)

VI = 4.5 V to 40 V, 5 mA ≤ IO ≤ 300 mA

198

(1)

External feedback resistor is not considered.

(2)

Design information — not tested, ensured by characterization.

6

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