6

PI6C4911510

Rev H

6/25/2015

PI6C4911510

2.5V/3.3V 1.5GHz Low Skew 1-to-10 Differential to

LVPECL Fanout Buffer w/ 2 to 1 Differential Clock Input Mux

Application Information

Wiring the differential input to accept single ended levels

generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of

R1 and R2 might need to be adjusted to postion the V_REF in the center of the input voltage swing. For example, if the input clock

Figure 1. Single-ended input to Differential input device

Single Ended

Clock Input

R1

1K

R2

1K

C1

0.1µ

CLK

/CLK

Power Supply Filtering Techniques

As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter perfor-

mance, power supply isolation is required. All power pins should be individually connected to the power supply plane through vias,

and 0.1μF an 1μF bypass capacitors should be used for each pin.

0.1µF

0.1µF

1µF

1µF

15-0077