1

2

3

4

8

7

6

5

VDD

IN

ENBL

AGND

VDD

OUT

OUT

PGND

UCC27321, UCC27322

UCC37321, UCC37322

www.ti.com

SLUS504H – SEPTEMBER 2002 – REVISED JANUARY 2016

5 Description (continued)

Using a design that inherently minimizes shoot-through current, the outputs of these can provide high gate drive

current where it is most needed at theMiller plateau region during the MOSFET switching transition. A unique

hybrid output stage paralleling bipolar and MOSFET transistors (TrueDrive) allows efficient current delivery at low

supply voltages. With this drive architecture, UCC3732x can be used in industry standard 6-A, 9-A and many 12-

A driver applications. Latch up and ESD protection circuitries are also included. Finally, the UCC3732x provides

an enable (ENBL) function to have better control of the operation of the driver applications. ENBL is implemented

active high logic and can be left open for standard operation.

In addition to the 8-pin SOIC (D) and 8-pin PDIP (P) package offerings, the UCC3732x also comes in the

thermally enhanced but tiny 8-pin MSOP PowerPAD™ (DGN) package. The PowerPAD package drastically

lowers the thermal resistance to extend the temperature operation range and improve the long-term reliability.

6 Pin Configuration and Functions

P, D, and DGN Packages

8-Pin PDIP, SOIC, and MSOP With PowerPAD

Top View

Pin Functions

PIN

I/O

DESCRIPTION

NAME

NO.

The AGND and the PGND must be connected by a single thick trace directly under the

device. There must be a low ESR, low ESL capacitor of 0.1 µF between VDD (pin 8) and

PGND and a separate 0.1-µF capacitor between VDD (pin 1) and AGND. The power

AGND

4

—

MOSFETs must be located on the PGND side of the device while the control circuit must be

on the AGND side of the device. The control circuit ground must be common with the AGND

while the PGND must be common with the source of the power FETs.

Enable input for the driver with logic compatible threshold and hysteresis. The driver output

ENBL

3

I

resistor for active high operation. When the device is disabled, the output state is, low

regardless of the input state.

IN

2

I

Input signal of the driver which has logic compatible threshold and hysteresis.

Driver outputs that must be connected together externally. The output stage is capable of

OUT

6, 7

O

providing 9-A peak drive current to the gate of a power MOSFET.

Common ground for output stage. This ground must be connected very closely to the source

PGND

5

—

of the power MOSFET which the driver is driving. Grounds are separated to minimize ringing

affects due to output switching di/dt which can affect the input threshold.

Supply voltage and the power input connections for this device. Two pins must be connected

VDD

1, 8

I

together externally.

Copyright © 2002–2016, Texas Instruments Incorporated

Submit Documentation Feedback

3