The following specifications apply for V

limits apply for T

Symbol

Parameter

Conditions

Typical

(Note 8)

Limits

(Note 9)

Units

(Limits)

T

C

Conversion Time (Not Including

f

8

1/f

MUX Addressing Time)

8

µs (max)

t

CA

Acquisition Time

1

1/f

t

SELECT

CLK High while CS is High

50

ns

t

SET-UP

CS Falling Edge or Data Input

25

ns (min)

Valid to CLK Rising Edge

t

HOLD

Data Input Valid after CLK Rising

Edge

20

ns (min)

t

CLK Falling Edge to Output Data

Valid (Note 15)

C

Data MSB First

250

ns (max)

Data LSB First

200

ns (max)

t

TRI-STATE Delay from Rising Edge

of CS to Data Output and SARS

Hi-Z

C

50

ns

(see TRI-STATE Test Circuits)

C

180

ns (max)

C

IN

Capacitance of Logic Inputs

5

pF

C

OUT

Capacitance of Logic Outputs

5

pF

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.

Note 2: Operating Ratings indicate conditions for which the device is functional. These ratings do not guarantee specific performance limits. For guaranteed speci-

fications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance character-

istics may degrade when the device is not operated under the listed test conditions.

5 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four

pins.

ADC08138.

Note 6: Human body model, 100 pF capacitor discharged through a 1.5 k

Ω resistor.

Note 7: See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or Linear Data Book section “Surface Mount” for other methods of soldering

surface mount devices.

Note 9: Guaranteed to National’s AOQL (Average Outgoing Quality Level).

ADC08138. See (Note 16).

Note 11: Cannot be tested for the ADC08131.

(e.g., 5V) can cause an input diode to conduct, especially at elevated temperatures. This will cause errors for analog inputs near full-scale. The specification allows

Note 13: Channel leakage current is measured after a single-ended channel is selected and the clock is turned off. For off channel leakage current the following two

nels is measured; two, with the selected channel tied low and the off channels tied high, total current flow through the off channels is again measured. The two cases

considered for determining on channel leakage current are the same except total current flow through the selected channel is measured.

Note 14: A40% to 60% duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limits

the minimum time the clock is high or low must be at least 450 ns. The maximum time the clock can be high or low is 100 µs.

Note 15: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in (see Block Diagram) to allow

for comparator response time.

reference current (700 µA typical, 2 mA maximum).

Note 17: Load regulation test conditions and specifications for the ADC08131 differ from those of the ADC08134 and ADC08138 because the ADC08131 has the

on-board reference as a permanent load.

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