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PI6LC48P0301LIE Datasheet(PDF) 9 Page - Pericom Semiconductor Corporation |
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PI6LC48P0301LIE Datasheet(HTML) 9 Page - Pericom Semiconductor Corporation |
9 / 12 page 9 www.pericom.com PI6LC48P0301 Rev. A 07/30/13 PI6LC48P0301 3-Output LVPECL Networking Clock Generator LVPECL Test Circuit Power Supply Filtering Techniques As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter perfor- mance, power supply isolation is required. The PI6LC48P0301 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and 0.1μF bypass capacitors should be used for each pin. Figure below illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10Ω resistor along with a 10μF bypass capacitor be connected to the VDDA pin. 50Ω 150Ω 0.01µF Z = 50Ω L = 0 ~ 10in 150Ω Device O Z = 50Ω O 50Ω 0.01µF VDD 0.1µF 0.1µF 10µF 10Ω * 3.3V or 2.5V VDDA * If VDD is 2.5V, the resistor value will be di erent, see app note for details 13-0116 |
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