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PI6LC48P25104LE Datasheet(PDF) 6 Page - Pericom Semiconductor Corporation |
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PI6LC48P25104LE Datasheet(HTML) 6 Page - Pericom Semiconductor Corporation |
6 / 7 page 6 www.pericom.com PI6LC48P25104 Rev. A 07/08/2013 PI6LC48P25104 Single Output LVPECL Clock Generator LVCMOS to XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in the figure below. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS signals, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resis- tance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of the two ways. First, R1 and R2 in parallel should equal the transmission line empedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. By overdriving the crystal oscillator, the device will be functional, but note, the device performance is quaranteed by using a quartz crystal. Thermal Information Symbol Description Condition Q JA Junction-to-ambient thermal resistance Still air 124.0 OC/W Q JC Junction-to-case thermal resistance 37.0 OC/W 13-0109 |
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