the analog supply pin should be minimized, keeping it below

200 mV

the power supply should be even more severely limited.

No pin should ever have a voltage on it that is in excess of

the supply voltages. This can be a problem upon application

of power to a circuit. Be sure that the supplies to circuits driv-

ing the CLK, OE, analog input and reference pins do not

come up any faster than does the voltage at the ADC08351

power pins.

3.0 LAYOUT AND GROUNDING

Proper grounding and proper routing of all signals is essen-

tial to ensure accurate conversion. Separate analog and

digital ground planes that are connected beneath the

ADC08351 are required to meet data sheet limits. The ana-

log and digital grounds may be in the same layer, but should

be separated from each other and should never overlap

each other.

Capacitive coupling between the typically noisy digital

ground plane and the sensitive analog circuitry can lead to

poor performance that may seem impossible to isolate and

remedy. The solution is to keep the analog circuitry well

separated from the digital circuitry and from the digital

ground plane.

Generally, analog and digital lines should cross each other at

90 degrees to avoid getting digital noise into the analog path.

To maximize accuracy in video (high frequency) systems,

however, avoid crossing analog and digital lines altogether.

Furthermore, it is important to keep any clock lines isolated

from ALL other lines, including other digital lines. Even the

generally accepted 90 degree crossing should be avoided as

even a little coupling can cause problems at high frequen-

cies.

Best performance at high frequencies and at high resolution

is obtained with a straight signal path. That is, the signal path

through all components should form a straight line wherever

possible.

Be especially careful with the layout of inductors. Mutual in-

ductance can change the characteristics of the circuit in

which they are used. Inductors should not be placed side by

side, even with just a small part of their bodies beside each

other.

The analog input should be isolated from noisy signal traces

to avoid coupling of spurious signals into the input. Any ex-

ternal component (e.g., a filter capacitor) connected be-

tween the converter’s input and ground should be connected

to a very clean point in the analog ground plane.

Figure 3 gives an example of a suitable layout. All analog cir-

cuitry (input amplifiers, filters, reference components, etc.)

should be placed on or over the analog ground plane. All

digital circuitry and I/O lines should be placed over the digital

ground plane.

All ground connections should have a low inductance path to

ground.

4.0 DYNAMIC PERFORMANCE

The ADC08351 is ac tested and its dynamic performance is

guaranteed. To meet the published specifications, the clock

source driving the CLK input must be free of jitter. For best

DS100895-25

FIGURE 3. Layout example showing separate analog and digital ground planes connected below the ADC08351.

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