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TPS65070RSLT Datasheet(PDF) 9 Page - Texas Instruments |
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TPS65070RSLT Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 98 page  TPS65070, TPS65072 TPS65073, TPS650731, TPS650732 www.ti.com SLVS950H – JULY 2009 – REVISED SEPTEMBER 2015 8.4 Thermal Information TPS65070x THERMAL METRIC(1) RSL (VQFN) UNIT 48 PINS RθJA Junction-to-ambient thermal resistance 30 °C/W RθJC(top) Junction-to-case (top) thermal resistance 16 °C/W RθJB Junction-to-board thermal resistance 5.3 °C/W ψJT Junction-to-top characterization parameter 0.2 °C/W ψJB Junction-to-board characterization parameter 5.3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 1 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 8.5 Electrical Characteristics VSYS = 3.6 V, EN_DCDCx = VSYS, L = 2.2 µH, COUT = 10 µF, TA = –40°C to 85°C typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT VINDCDC Input voltage range for DC-DC converters 2.8 6.3 V Only DCDC2, DCDC3 and LDO1 enabled, device in ON- 140 mode; DCDC converters in PFM Per DC/DC converter, PFM mode 19 30 µA Operating quiescent current For LDO1 or LDO2 (either one enabled) 20 35 IQ Total current into VSYS, VINDCDCx, VINLDO1/2 For LDO1 and LDO2 (both enabled) 34 For wLED converter 1.5 mA Per DC/DC converter, PWM mode 2.5 All converters, LDOs, wLED driver and ADC disabled, no ISD Shutdown current input voltage at AC and USB; 8 12 µA SYS voltage turned off –2% 2.8 2% Voltage at the output of the power manager detected at pin 3 VUVLO Undervoltage lockout threshold SYS; falling voltage, voltage defined with <UVLO0>, V 3.1 <UVLO1> DEFAULT: 3 V 3.25 360 Rising voltage defined with <UVLO hysteresis>; DEFAULT: Undervoltage lockout hysteresis mV 500 mV 450 Undervoltage lockout deglitch time Due to internal delay 4 ms Thermal shutdown for DCDC converters, wLED TSD Increasing junction temperature 150 °C driver and LDOs Thermal shutdown hysteresis Decreasing junction temperature 20 °C EN_DCDC1, EN_DCDC2, EN_DCDC3, DEFDCDC2, DEFDCDC3, SDAT, SCLK, EN_wLED (optional) High Level Input Voltage, EN_DCDC1, VIH EN_DCDC2, EN_DCDC3, DEFDCDC2, 1.2 VSYS V DEFDCDC3, SDAT, SCLK, EN_wLED Low Level Input Voltage, EN_DCDC1, VIL EN_DCDC2, EN_DCDC3, DEFDCDC2, 0 0.4 V DEFDCDC3, SDAT, SCLK, EN_wLED Input bias current, EN_DCDC1, EN_DCDC2, IIN EN_DCDC3, DEFDCDC2, DEFDCDC3, SDAT, 0.01 1 µA SCLK Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: TPS65070 TPS65072 TPS65073 TPS650731 TPS650732 |
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