OSCILLATOR

1.41

f

RC

=

UCC2808-1, UCC2808-2, UCC3808-1, UCC3808-2

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SLUS168E – APR 1999 – REVISED AUGUST 2015

Feature Description (continued)

where

•

frequency is in hertz, resistance in ohms, and capacitance in farads.

(1)

The recommended range of timing resistors is between 10 k

Ω and 200 kΩ and range of timing capacitors is

between 100 pF and 1000 pF. Timing resistors less than 10 k

Ω must be avoided.

For best performance, keep the timing capacitor lead to GND as short as possible, the timing resistor lead from

VDD as short as possible, and the leads between timing components and RC as short as possible. Separate

ground and VDD traces to the external timing network are encouraged.

VDD: The power input connection for this device. Although quiescent VDD current is very low, total supply

current will be higher, depending on OUTA and OUTB current, and the programmed oscillator frequency. Total

VDD current is the sum of quiescent VDD current and the average OUT current. Knowing the operating

frequency and the MOSFET gate charge (Qg), average OUT current can be calculated from:

where

•

F is frequency To prevent noise problems, bypass VDD to GND with a ceramic capacitor as close to the chip

as possible along with an electrolytic capacitor.

(2)

A 1-

μF decoupling capacitor is recommended.

7.4 Device Functional Modes

7.4.1 VCC

When VCC becomes above 12.5 V (for UCCx808-1) or 4.3 V (for UCCx808-2), the device is enable, and after all

fault conditions are cleared, the gate driver starts with soft-start. When VCC drops below 8.3 V (for UCCx808-1)

or 4.1 V (for UCCx808-2), the device enters the UVLO protection mode and both gate drivers are actively pulled

low.

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Product Folder Links: UCC2808-1 UCC2808-2 UCC3808-1 UCC3808-2