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TMS320C6657CZH Datasheet(PDF) 4 Page - Texas Instruments |
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TMS320C6657CZH Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 245 page  TMS320C6655, TMS320C6657 SPRS814B – MARCH 2012 – REVISED APRIL 2015 www.ti.com Table of Contents 1 C665x Features and Description ..................... 1 7.2 Recommended Operating Conditions ............. 113 1.1 Features .............................................. 1 7.3 Electrical Characteristics ........................... 114 1.2 KeyStone Architecture ................................ 1 7.4 Power Supply to Peripheral I/O Mapping ......... 115 1.3 Trademarks ........................................... 2 8 Peripheral Information and Electrical Specifications ......................................... 116 1.4 Device Description ................................... 2 8.1 Recommended Clock and Control Signal Transition 1.5 Functional Block Diagram ............................ 3 Behavior ............................................ 116 2 Revision History ........................................ 5 8.2 Power Supplies .................................... 116 3 Device Overview ......................................... 6 8.3 Power Sleep Controller (PSC) ..................... 124 3.1 Device Characteristics ................................ 6 8.4 Reset Controller .................................... 128 3.2 DSP Core Description ................................ 7 8.5 Main PLL and PLL Controller ...................... 134 3.3 Memory Map Summary ............................. 10 8.6 DDR3 PLL .......................................... 151 3.4 Boot Sequence ...................................... 14 8.7 Enhanced Direct Memory Access (EDMA3) 3.5 Boot Modes Supported and PLL Settings ........... 15 Controller ........................................... 154 3.6 PLL Boot Configuration Settings .................... 37 8.8 Interrupts ........................................... 158 3.7 Second-Level Bootloaders .......................... 37 8.9 Memory Protection Unit (MPU) .................... 183 3.8 Terminals ............................................ 38 8.10 DDR3 Memory Controller .......................... 198 3.9 Terminal Functions .................................. 43 8.11 I2C Peripheral ...................................... 199 3.10 Development and Support .......................... 65 8.12 I2C Timing Requirements ......................... 202 3.11 Related Documentation from Texas Instruments ... 67 8.13 SPI Peripheral ...................................... 204 4 Device Configuration .................................. 68 8.14 HyperLink Peripheral ............................... 207 4.1 Device Configuration at Device Reset .............. 68 8.15 UART Peripheral ................................... 211 4.2 Peripheral Selection After Device Reset ............ 69 8.16 PCIe Peripheral .................................... 212 4.3 Device State Control Registers ..................... 69 8.17 EMIF16 Peripheral ................................. 213 4.4 Pullup/Pulldown Resistors .......................... 96 8.18 Ethernet Media Access Controller (EMAC) ........ 216 5 System Interconnect ................................... 97 8.19 Management Data Input/Output (MDIO) ........... 222 5.1 Internal Buses and Switch Fabrics .................. 97 8.20 Timers .............................................. 224 5.2 Switch Fabric Connections Matrix .................. 97 8.21 General-Purpose Input/Output (GPIO) ............. 225 5.3 TeraNet Switch Fabric Connections ............... 100 8.22 Semaphore2 ....................................... 226 5.4 Bus Priorities ....................................... 103 8.23 Multichannel Buffered Serial Port (McBSP) ........ 226 6 C66x CorePac .......................................... 105 8.24 Universal Parallel Port (uPP) ...................... 231 6.1 Memory Architecture ............................... 106 8.25 Serial RapidIO (SRIO) Port ........................ 235 6.2 Memory Protection ................................. 109 8.26 Turbo Decoder Coprocessor (TCP3d) ............. 236 6.3 Bandwidth Management ........................... 110 8.27 Enhanced Viterbi-Decoder Coprocessor (VCP2) .. 236 6.4 Power-Down Control ............................... 110 8.28 Emulation Features and Capability ................ 236 6.5 C66x CorePac Revision ........................... 111 8.29 Related Links ...................................... 239 6.6 C66x CorePac Register Descriptions .............. 111 9 Mechanical Data ....................................... 240 7 Device Operating Conditions ....................... 112 9.1 Thermal Data ...................................... 240 7.1 Absolute Maximum Ratings ........................ 112 9.2 Packaging Information ............................. 240 4 Table of Contents Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback |
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