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ADC1038 Datasheet(PDF) 3 Page - National Semiconductor (TI) |
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ADC1038 Datasheet(HTML) 3 Page - National Semiconductor (TI) |
3 / 13 page Electrical Characteristics (Continued) The following specifications apply for V CC = +5.0V, VREF = +4.6V, fS = 700 kHz, and fC = 3 MHz unless otherwise specified. Boldface limits apply for T A = TJ = TMIN to TMAX ; all other limits TA = TJ = 25˚C. Symbol Parameter Conditions Typical Limit Units (Note 8) (Note 9) (Limits) AC CHARACTERISTICS f C Conversion Clock (C CLK) 0.7 MHz (min) Frequency 4.0 3.0 MHz (max) f S Serial Data Clock (S CLK)fC = 3 MHz, R/L = “0” 183 kHz (min) Frequency (Note 13) f C = 3 MHz, R/L = “1” 622 kHz (min) f C = 3 MHz, R/L = “0” or R/L = “1” 2 1.0 MHz (max) T C Conversion Time Not Including MUX Addressing and 41 (1/f C) (max) Analog Input Sampling Times + 200 ns t CA Analog Sampling Time After Address is Latched,CS = Low 4.5 (1/f S) (max) + 200 ns t ACC Access Time Delay from CS or OE OE = “0” 100 200 ns (max) Falling Edge to DO Data Valid t SET-UP Set-up Time of CS Falling 75 150 ns (min) Edge to S CLK Rising Edge t 1H,t0H Delay from OE or CS Rising R L = 3kΩ,CL = 100 pF 100 120 ns (max) Edge to DO TRI-STATE t HDI DI Hold Time from S CLK Rising Edge 0 50 ns (min) t SDI DI Set-up Time to S CLK Rising Edge 50 100 ns (min) t HDO DO Hold Time from S CLK Falling Edge R L = 30 kΩ,CL = 100 pF 70 10 ns (min) t DDO Delay from S CLK Falling R L = 30 kΩ,CL = 100 pF 150 250 ns (max) Edge to DO Data Valid t RDO DO Rise Time R L = 30 kΩ, TRI-STATE to High 35 75 ns (max) C L = 100 pF Low to High 75 150 ns (max) t FDO DO Fall Time R L = 30 kΩ, TRI-STATE to Low 35 75 ns (max) C L = 100 pF High to Low 75 150 ns (max) C IN Input Capacitance Analog Inputs (CH0–CH7) 50 pF All Other Inputs 7.5 pF Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Note 2: Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may de- grade when the device is not operated under the listed test conditions. Note 3: All voltages are measured with respect to AGND and DGND, unless otherwise specified. Note 4: When the input voltage (VIN) at any pin exceeds the power supplies (VIN < DGND, or VIN > VCC) the current at that pin should be limited to 5 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four pins. Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax, θJA and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJmax −TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, TJmax = 125˚C. The typical thermal resistance (θJA) when board mounted is 64˚C/W. Note 6: Human body model, 100 pF capacitor discharged through a 1.5 k Ω resistor. Note 7: See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or Linear Databook section “Surface Mount” for other methods of soldering surface mount devices. Note 8: Typicals are at TJ = 25˚C and represent most likely parametric norm. Note 9: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 10: Total unadjusted error includes offset, full-scale, linearity, multiplexer, and hold step errors. Note 11: Two on-chip diodes are tied to each analog input. They will forward-conduct for analog input voltages one diode drop below ground or one diode drop greater than VCC supply. Be careful during testing at low VCC levels (4.5V), as high level analog inputs (5V) can cause an input diode to conduct, especially at el- evated temperatures, which will cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode; this means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct. Exceeding this range on an unselected channel will corrupt the reading of a selected channel. To achieve an absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over tem- perature variations, initial tolerance and loading. Note 12: Channel leakage current is measured after the channel selection. Note 13: In order to synchronize the serial data exchange properly, SARS needs to go low after completion of the serial I/O data exchange. If this does not occur the output shift register will be reset and the correct output data lost. The minimum limit for SCLK will depend on CCLK frequency and whether right-justified or left-justified, and can be determined by the following equations: f S > (8.5/41) (fC) with right-justification (R/L = “1”) and fS > (2.5/41) (fC) with left-justification (R/L = “0”). www.national.com 3 |
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