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IS25CD025-JDLA Datasheet(PDF) 8 Page - Integrated Silicon Solution, Inc

Part # IS25CD025-JDLA
Description  256Kbit Single Operating Voltage Serial Flash Memory
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Manufacturer  ISSI [Integrated Silicon Solution, Inc]
Direct Link  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS25CD025-JDLA Datasheet(HTML) 8 Page - Integrated Silicon Solution, Inc

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IS25CD025
Integrated Silicon Solution, Inc.- www.issi.com
Rev. G
07/31/2013
8
REGISTERS (CONTINUED)
PROTECTION MODE
The IS25CD025 have two types of write-protection
mechanisms: hardware and software. These are used
to prevent irrelevant operation in a possibly noisy
environment and protect the data integrity.
HARDWARE WRITE-PROTECTION
The devices provide two hardware write-protection
features:
a. When inputting a program, erase or write status
register instruction, the number of clock pulse is
checked to determine whether it is a multiple of eight
before the executing. Any incomplete instruction
command sequence will be ignored.
b. The Write Protection (WP#) pin provides a
hardware write protection method for BP2, BP1, BP0
and SRWD in the Status Register. Refer to the
STATUS REGISTER description.
c.
Write inhibit is 2.4V, all write sequence will be
ignored when Vcc drop to 2.4V and lower
SOFTWARE WRITE PROTECTION
The IS25CD025 also provides two software write
protection features:
a. Before the execution of any program, erase or write
status register instruction, the Write Enable Latch
(WEL) bit must be enabled by executing a Write
Enable (WREN) instruction. If the WEL bit is not
enabled first, the program, erase or write register
instruction will be ignored.
b. The Block Protection (BP2, BP1, BP0) bits allow part
or the whole memory area to be write-protected.
Table 9. Hardware Write Protection on Status
Register
SRWD
WP#
Status Register
0
Low
Writable
1
Low
Protected
0
High
Writable
1
High
Writable


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