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IS25WD040-JBLA Datasheet(PDF) 2 Page - Integrated Silicon Solution, Inc |
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IS25WD040-JBLA Datasheet(HTML) 2 Page - Integrated Silicon Solution, Inc |
2 / 35 page IS25WD020/040 Integrated Silicon Solution, Inc.- www.issi.com Rev. F 07/31/2013 2 CONNECTION DIAGRAMS PIN DESCRIPTIONS SYMBOL TYPE DESCRIPTION CE# INPUT Chip Enable: CE# low activates the devices internal circuitries for device operation. CE# high deselects the devices and switches into standby mode to reduce the power consumption. When a device is not selected, data will not be accepted via the serial input pin (Sl), and the serial output pin (SO) will remain in a high impedance state. SCK INPUT Serial Data Clock SIO INPUT/OUTPUT Serial Data Input/Output SO OUTPUT Serial Data Output GND Ground Vcc Device Power Supply WP# INPUT Write Protect: A hardware program/erase protection for all or part of a memory array. When the WP# pin is low, memory array write-protection depends on the setting of BP2, BP1 and BP0 bits in the Status Register. When the WP# is high, the devices are not write-protected. HOLD# INPUT Hold: Pause serial communication by the master device without resetting the serial sequence. CE# CE# SO WP# GND Vcc HOLD# SCK SIO SIO SCK HOLD# Vcc SO WP# GND 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 8-Pin SOIC/VVSOP 8-Contact WSON |
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