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IS45R32160F Datasheet(PDF) 2 Page - Integrated Silicon Solution, Inc |
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IS45R32160F Datasheet(HTML) 2 Page - Integrated Silicon Solution, Inc |
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2 / 68 page  2 Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 11/5/2013 IS42/45R86400F/16320F/32160F, IS42/45S86400F/16320F/32160F DEVICE OVERVIEW The 512Mb SDRAM is a high speed CMOS, dynamic random-accessmemorydesignedtooperateineither3.3V Vdd/Vddq or2.5VVdd/Vddq memory systems, depending on the DRAM option. Internally configured as a quad-bank DRAM with a synchronous interface. The512MbSDRAM(536,870,912bits)includesanAUTO REFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of theclocksignal,CLK.AllinputsandoutputsareLVTTL compatible. The512MbSDRAMhastheabilitytosynchronouslyburst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access. A self-timed row precharge initiated at the end of the burst sequenceisavailablewiththeAUTOPRECHARGEfunction enabled. Precharge one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. SDRAM read and write accesses are burst oriented starting at a selected location and continuing for a programmed number of locations in a programmed sequence.The registration of an ACTIVE command begins accesses, followedbyaREADorWRITEcommand.TheACTIVE command in conjunction with address bits registered are usedtoselectthebankandrowtobeaccessed(BA0, BA1selectthebank;A0-A12selecttherow).TheREAD or WRITE commands in conjunction with address bits registered are used to select the starting column location for the burst access. ProgrammableREADorWRITEburstlengthsconsistof 1, 2, 4 and 8 locations or full page, with a burst terminate option. CLK CKE CS RAS CAS WE A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BA0 BA1 A10 A12 COMMAND DECODER & CLOCK GENERATOR MODE REGISTER REFRESH CONTROLLER REFRESH COUNTER SELF REFRESH CONTROLLER ROW ADDRESS LATCH COLUMN ADDRESS LATCH BURST COUNTER COLUMN ADDRESS BUFFER COLUMN DECODER DATA IN BUFFER DATA OUT BUFFER DQML DQMH DQ 0-15 VDD/VDDQ Vss/VssQ 13 13 10 13 13 10 16 16 16 16 1024 (x 16) 8192 8192 8192 8192 MEMORY CELL ARRAY BANK 0 SENSE AMP I/O GATE BANK CONTROL LOGIC ROW ADDRESS BUFFER A11 2 FUNCTIONAL BLOCK DIAGRAM (FOR 8MX16X4 BANKS SHOWN) |
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