IS42/45R86400F/16320F/32160F

IS42/45S86400F/16320F/32160F

Integrated Silicon Solution, Inc. — www.issi.com

1

Rev. 00A

11/5/2013

Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time with-

out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain

the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can

reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such ap-

plications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

FEATURES

• Clock frequency: 200, 166, 143 MHz

• Fullysynchronous;allsignalsreferencedtoa

positive clock edge

• Internalbankforhidingrowaccess/precharge

• LVTTLinterface

• Programmableburstlength

– (1, 2, 4, 8, full page)

• Programmableburstsequence:

Sequential/Interleave

• AutoRefresh(CBR)

• SelfRefresh

• 8Krefreshcyclesevery64ms

• Randomcolumnaddresseveryclockcycle

• ProgrammableCAS latency (2, 3 clocks)

• Burstread/writeandburstread/singlewrite

operations capability

• Burstterminationbyburststopandprecharge

command

• Packages:

x8/x16:54-pinTSOP-II,54-ballTF-BGA(x16only)

x32:90-ballTF-BGA,86-pinTSOP-ll

• TemperatureRange:

16Mx32, 32Mx16, 64Mx8

512Mb SDRAM

ADVANCED INFORMATION

NOVEMBER 2013

KEY TIMING PARAMETERS

Parameter

-5

-6

-7

Unit

ClkCycleTime

CAS

Latency=3

5

6

7

ns

CAS

Latency=2

10

10

7.5

ns

ClkFrequency

CAS

Latency=3

200

167

143

Mhz

CAS

Latency=2

100

100

133

Mhz

AccessTimefromClock

CAS

Latency=3

5.0

5.4

5.4

ns

CAS

Latency=2

6

6

5.4

ns

ADDRESS TABLE

Parameter

16M x 32

32M x 16

64M x 8

Configuration

4M x 32 x 4

banks

8M x 16 x 4

banks

16M x 8 x 4

banks

BankAddress

Pins

BA0,BA1

BA0,BA1

BA0,BA1

Autoprecharge

Pins

A10/AP

A10/AP

A10/AP

Row Address

8K(A0–A12) 8K(A0–A12) 8K(A0–A12)

Column

Address

512(A0 – A8)

1K(A0–A9)

2K(A0–A9,

A11)

Refresh Count

Com./Ind./A1

A2

8K/64ms

8K/16ms

8K/64ms

8K/16ms

8K/64ms

8K/16ms

DEVICE OVERVIEW

data transfer using pipeline architecture. All inputs and

outputs signals refer to the rising edge of the clock input.

The512MbSDRAMisorganizedasfollows.

IS42/45S32160D

IS42/45S16320D

IS42/45S86400D

IS42/45R32160D

IS42/45R16320D

IS42/45R86400D

4M x 32 x 4 banks

8M x 16 x 4 banks

16M x 8 x 4 banks

90-ballTF-BGA

54-pinTSOP-II

54-pinTSOP-II

86-pinTSOP-ll

54-ballTF-BGA

PACKAGE INFORMATION