Integrated Silicon Solution, Inc. — www.issi.com

1

Rev. A

12/06/2011

Copyright©2011IntegratedSiliconSolution,Inc.Allrightsreserved.ISSIreservestherighttomakechangestothisspecificationanditsproductsatanytimewithoutnotice.ISSIassumesno

liabilityarisingoutoftheapplicationoruseofanyinformation,productsorservicesdescribedherein.Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingon

anypublishedinformationandbeforeplacingordersforproducts.

IntegratedSiliconSolution,Inc.doesnotrecommendtheuseofanyofitsproductsinlifesupportapplicationswherethefailureormalfunctionoftheproductcanreasonablybeex-

pectedtocausefailureofthelifesupportsystemortosignificantlyaffectitssafetyoreffectiveness.ProductsarenotauthorizedforuseinsuchapplicationsunlessIntegratedSilicon

Solution,Inc.receiveswrittenassurancetoitssatisfaction,that:

a.)theriskofinjuryordamagehasbeenminimized;

b.)theuserassumeallsuchrisks;and

c.)potentialliabilityofIntegratedSiliconSolution,Incisadequatelyprotectedunderthecircumstances

IS42S16402J

IS45S16402J

FEATURES

• Clockfrequency:200,166,143,133MHz

• Fullysynchronous;allsignalsreferencedtoa

positiveclockedge

• Internalbankforhidingrowaccess/precharge

• Single3.3Vpowersupply

• LVTTLinterface

• Reducedstrengthoutputdrive:12-15mA

• Programmableburstlength

–(1,2,4,8,fullpage)

• Programmableburstsequence:

Sequential/Interleave

• Selfrefreshmodes

• Autorefresh(CBR)

• 4096refreshcyclesevery64ms(Com,Ind,A1

grade)or16ms(A2grade)

• Randomcolumnaddresseveryclockcycle

• ProgrammableCASlatency(2,3clocks)

• Burstread/writeandburstread/singlewrite

operationscapability

• Burstterminationbyburststopandprecharge

command

OPTIONS

• Package:

54-pinTSOPII

54-ballTF-BGA(8mmx8mm)

60-ballTF-BGA(10.1mmx6.4mm)

• OperatingTemperatureRange

OVERVIEW

bits x 16-bit x 4-bank for improved performance. The

synchronous DRAMs achieve high-speed data transfer

usingpipelinearchitecture.Allinputsandoutputssignals

refertotherisingedgeoftheclockinput.

1 Meg Bits x 16 Bits x 4 Banks (64-MBIT)

SYNCHRONOUS DYNAMIC RAM

DECEMBER 2011

KEY TIMING PARAMETERS

Parameter

-5

-6

-7

Unit

ClkCycleTime

CAS

Latency=3

5

6

7

ns

CAS

Latency=2

10

10

7.5

ns

ClkFrequency

CAS

Latency=3

200

166

143

Mhz

CASLatency=2

100

100

133

Mhz

AccessTimefromClock

CAS

Latency=3

5

5.4

5.4

ns

CAS

Latency=2

8

8

5.4

ns

Parameter

4M x 16

Configuration

1M x 16 x 4

banks

Refresh Count

Com./Ind.

A1

A2

4K/64ms

4K/64ms

4K/16ms

Row Addresses

A0-A11

Column Addresses

A0-A7

Bank Address Pins

BA0, BA1

Auto Precharge Pins

A10/AP

ADDRESS TABLE