Integrated Silicon Solution, Inc. - www.issi.com

1

Rev. A

07/18/2012

Copyright © 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without

notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-

est version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-

ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications

unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

IS42S32800G

IS45S32800G

FEATURES

• Clockfrequency:200,166,143MHz

• Fullysynchronous;allsignalsreferencedtoa

positive clock edge

• Internalbankforhidingrowaccess/precharge

• SinglePowersupply:3.3V+0.3V

• LVTTLinterface

• Programmableburstlength

–(1,2,4,8,fullpage)

• Programmableburstsequence:

Sequential/Interleave

• AutoRefresh(CBR)

• SelfRefresh

• 4096refreshcyclesevery16ms(A2grade)or

64ms(Commercial,Industrial,A1grade)

• Randomcolumnaddresseveryclockcycle

• ProgrammableCASlatency(2,3clocks)

• Burstread/writeandburstread/singlewrite

operations capability

• Burstterminationbyburststopandprecharge

command

OPTIONS

• Package:

90-ballTF-BGA

• OperatingTemperatureRange:

OVERVIEW

data transfer using pipeline architecture. All inputs and

outputs signals refer to the rising edge of the clock input.

The 256Mb SDRAM is organized in 2Meg x 32 bit x 4

Banks.

8M x 32

256Mb SYNCHRONOUS DRAM

AUGUST 2012

KEY TIMING PARAMETERS

Parameter

-5

-6

-7

Unit

ClkCycleTime

CAS

Latency=3

5

6

7

ns

CAS

Latency=2

10

10

7.5

ns

ClkFrequency

CAS

Latency=3

200

166

143

Mhz

CAS

Latency=2

100

100

133

Mhz

AccessTimefromClock

CAS

Latency=3

4.8

5.4

5.4

ns

CAS

Latency=2

6.5

6.5

5.5

ns

ADDRESS TABLE

Parameter

8M x 32

Configuration

2Mx32x4banks

RefreshCount

Com./Ind.

A1

A2

4K/64ms

4K/64ms

4K/16ms

RowAddresses

A0 – A11

Column

Addresses

A0 – A8

BankAddress

Pins

BA0,BA1

Autoprecharge

Pins

A10/AP