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IS46LR32400G Datasheet(PDF) 1 Page - Integrated Silicon Solution, Inc

Part # IS46LR32400G
Description  Four internal banks for concurrent operation
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Manufacturer  ISSI [Integrated Silicon Solution, Inc]
Direct Link  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS46LR32400G Datasheet(HTML) 1 Page - Integrated Silicon Solution, Inc

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IS43/46LR32400G
Advanced Information
1
Rev. 00A | June 2014
www.issi.com - dram@issi.com
1M x 32Bits x 4Banks Mobile DDR SDRAM
Description
The IS43/46LR32400G is 134,217,728 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 1,048,576 words x
32 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data Input/ Output signals are transmitted
on a 32-bit bus. The double data rate architecture is essentially a 2
N prefetch architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock.
The data paths are internally pipelined and 2n-bits prefetched to achieve very high bandwidth. All input and output voltage levels are
compatible with LVCMOS.
Features
• JEDEC standard 1.8V power supply.
• VDD = 1.8V, VDDQ = 1.8V
• Four internal banks for concurrent operation
• MRS cycle with address key programs
- CAS latency 2, 3 (clock)
- Burst length (2, 4, 8, 16)
- Burst type (sequential & interleave)
• Fully differential clock inputs (CK, /CK)
• All inputs except data & DM are sampled at the rising
edge of the system clock
• Data I/O transaction on both edges of data strobe
• Bidirectional data strobe per byte of data (DQS)
• DM for write masking only
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• 64ms refresh period (4K cycle)
• Auto & self refresh
• Concurrent Auto Precharge
• Maximum clock frequency up to 200MHZ
• Maximum data rate up to 400Mbps/pin
• Power Saving support
- PASR (Partial Array Self Refresh)
- Auto TCSR (Temperature Compensated Self Refresh)
- Deep Power Down Mode
- Programmable Driver Strength Control by Full Strength
or ¾, ½, ¼, ⅛ of Full Strength
• LVCMOS compatible inputs/outputs
• 90-Ball FBGA package
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its
products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services
described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information
and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or
effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to
its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances


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