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LDC1312QDNTRQ1 Datasheet(PDF) 7 Page - Texas Instruments |
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LDC1312QDNTRQ1 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 56 page  SCL SDA tHD;STA tLOW tr tHD;DAT tHIGH tf tSU;DAT tSU;STA tSU;STO tf START REPEATED START STOP tHD;STA START tSP tr tBUF 7 LDC1312-Q1, LDC1314-Q1 www.ti.com SNOSCZ6 – APRIL 2016 Product Folder Links: LDC1312-Q1 LDC1314-Q1 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated 7.6 Timing Characteristics MIN NOM MAX UNIT tWAKEUP Wake-up Time from SD high-low transition to I2C readback 2 ms tWD-TIMEOUT Sensor recovery time (after watchdog timeout) 5.2 ms (1) This parameter is specified by design and/or characterization and is not tested in production. 7.7 Switching Characteristics - I2C Unless otherwise specified, all limits ensured for TA = 25°C, VDD = 3.3 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOLTAGE LEVELS VIH Input High Voltage 0.7 ˣVDD V VIL Input Low Voltage 0.3 ˣVDD V VOL Output Low Voltage (3mA sink current) 0.4 V HYS Hysteresis 0.1 ˣVDD V I2C TIMING CHARACTERISTICS fSCL Clock Frequency 10 400 kHz tLOW Clock Low Time 1.3 μs tHIGH Clock High Time 0.6 μs tHD;STA Hold Time (repeated) START condition After this period, the first clock pulse is generated 0.6 μs tSU;STA Set-up time for a repeated START condition 0.6 μs tHD;DAT Data hold time 0 μs tSU;DAT Data setup time 100 ns tSU;STO Set-up time for STOP condition 0.6 μs tBUF Bus free time between a STOP and START condition 1.3 μs tVD;DAT Data valid time 0.9 μs tVD;ACK Data valid acknowledge time 0.9 μs tSP Pulse width of spikes that must be suppressed by the input filter(1) 50 ns Figure 1. I2C Timing |
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