IS61DDB22M18A

IS61DDB21M36A

Integrated Silicon Solution, Inc.- www.issi.com

Rev. B

10/02/2014

5

The write data is provided in a ‘late write’ mode; that is, the data-in corresponding to the first address of the burst, is

presented one cycle later or at the rising edge of the following K clock. The data-in corresponding to the second write

burst address follows next, registered by the rising edge of K#.

The data-in provided for writing is initially kept in write buffers. The information on these buffers is written into the array

on the third write cycle. A read cycle to the last two write address produces data from the write buffers. Similarly, a

read address followed by the same write address produces the latest write data. The SRAM maintains data coherency.

During a write, the byte writes independently control which byte of any of the two burst addresses is written (see

X18/X36 Write Truth Tables and Timing Reference Diagram for Truth Table).

Whenever a write is disabled (R/W# is high at the rising edge of K), data is not written into the memory.

RQ Programmable Impedance

its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the

SRAM. For example, an RQ of 250Ω results in a driver impedance of 50Ω. The allowable range of RQ to guarantee

impeda

nce matching is between 175Ω and 350Ω at V

away from the ZQ ball on the SRAM module. The capacitance of the loaded ZQ trace must be less than 7.5pF.

The ZQ pin can also be directly connected to V

DDQ

to obtain a minimum impedance setting. ZQ should not be

connected to V

SS

.

Programmable Impedance and Power-Up Requirements

Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by drifts in

supply voltage and temperature. During power-up, the driver impedance is in the middle of allowable impedances

values. The final impedance value is achieved within 1024clock cycles.

Clock Consideration

This device uses an internal DLL for maximum output data valid window. It can be placed in a stopped-clock mode to

operating range.

Single Clock Mode

This device can be also operated in single-clock mode. In this case, C and C# are both connected high at power-up

and must never change. Under this condition, K and K# control the output timings. Either clock pair must have both

Delay Locked Loop (DLL)

Delay Lock Loop (DLL) is a new system to align the output data coincident with clock rising or falling edge to enhance

the output valid timing characteristics. It is locked to the clock frequency and is constantly adjusted to match the clock

frequency. Therefore device can have stable output over the temperature and voltage variation.

DLL has a limitation of locking range and jitter adjustment which are specified as tKHKH and tKCvar respectively in the

AC timing characteristics. In order to turn this feature off, applying logic low to the Doff# pin will bypass this. In the DLL

off mode, the device behaves with one cycle latency and a longer access time which is known in DDR-I or legacy

QUAD mode.

The DLL can also be reset without power down by toggling Doff# pin low to high or stopping the input clocks K and K#

for a minimum of 30ns.(K and K# must be stayed either at higher than VIH or lower than VIL level. Remaining Vref is

not permitted.) DLL reset must be issued when power up or when clock frequency changes abruptly. After DLL being

reset, it gets locked after 2048 cycles of stable clock.