IS61DDB24M18A

IS61DDB22M36A

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

08/15/2014

9

State Diagram

Power-Up

NOP

Load New Read Address

DDR-II Read

DDR-II Write

Load

Load

Load

Read

Write

/LOAD

/LOAD

/Load

Notes:

1.

Internal burst counter is fixed as two-bit linear; that is, when first address is A0+0, next internal burst address is A0+1.

2.

Read refers to read active status with R/W# = High.

3.

Write refers to write active status with R/W# = LOW.

4.

Load refers to read new address active status with LD# = low.

5.

Load is read new address inactive status with LD = high.

Linear Burst Sequence Table

Burst Sequence

Case1

Case2

First Address

0

1

Second Address

1

0