IS61LPS51236B/IS61VPS51236B/IS61VVPS51236B

IS61LPS102418B/IS61VPS102418B/IS61VVPS102418B

Integrated Silicon Solution, Inc.- www.issi.com

Rev. B

10/16/2014

8

1024K x 18, 100PIN QFP (Top View)

NC

1

80

A

NC

2

79

NC

NC

3

78

NC

VDDQ

4

77

VDDQ

VSS

5

76

VSS

NC

6

75

NC

NC

7

74

DQPa

DQb

8

73

DQa

DQb

9

72

DQa

VSS

10

71

VSS

VDDQ

11

70

VDDQ

DQb

12

69

DQa

DQb

13

68

DQa

NC

14

67

VSS

VDD

15

66

NC

NC

16

65

VDD

VSS

17

64

ZZ

DQb

18

63

DQa

DQb

19

62

DQa

VDDQ

20

61

VDDQ

VSS

21

60

VSS

DQb

22

59

DQa

DQb

23

58

DQa

DQPb

24

57

NC

NC

25

56

NC

VSS

26

55

VSS

VDDQ

27

54

VDDQ

NC

28

53

NC

NC

29

52

NC

NC

30

51

NC

1024K x 18

Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.

PIN DESCRIPTIONS

Symbol

Pin Name

Symbol

Pin Name

CLK

Synchronous Clock

/GW

Global Write Enable

A0,A1

Synchronous Burst Address Inputs

/OE

Output Enable

A

Address Inputs

DQx

Data Inputs/Outputs

/ADV

Synchronous Burst Address Advance

ZZ

Power Sleep Mode

/ADSP

Address Status Processor

NC

No Connect

/ADSC

Address Status Controller

Power Supply

MODE

Burst Sequence Selection

I/O Power Supply

/CE,CE2,/CE2

Synchronous Chip Enable

Ground

/BWE

Byte Write Enable

/BWx (x=a-b)

Synchronous Byte Write Inputs