IS61VPS102418B datasheet(10/33 Pages) ISSI

Part #	IS61VPS102418B

Description	Internal self-timed write cycle

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Manufacturer	ISSI [Integrated Silicon Solution, Inc]

Direct Link	http://www.issi.com

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IS61LPS51236B/IS61VPS51236B/IS61VVPS51236B

IS61LPS102418B/IS61VPS102418B/IS61VVPS102418B

Integrated Silicon Solution, Inc.- www.issi.com

Rev. B

10/16/2014

10

PARTIAL TRUTH TABLE

Operation

/GW

/BWE

/BWa

/BWb

/BWc

/BWd

READ

H

X

READ

H

L

H

WRITE BYTE a

H

L

H

WRITE BYTE b

H

L

H

L

H

WRITE BYTE c

H

L

H

L

H

WRITE BYTE d

H

L

H

L

WRITE ALL BYTEs

H

L

WRITE ALL BYTEs

L

X

Notes:

1.

X means "Don't Care".

2.

All inputs in this table must beet setup and hold time around the rising edge of CLK.

ADDRESS SEQUENCE IN BURST MODE

INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or NC)

External Address

1st Burst Address

2nd Burst Address

3rd Burst Address

A1 A0

00

01

10

11

01

00

11

10

11

00

01

11

10

01

00

LINEAR BURST ADDRESS TABLE (MODE = Vss )

Power Up Sequence

VDDQ

→ VDD1 → I/O Pins2

Notes:

1.

VDD can be applied at the same time as VDDQ

2.

Applying I/O inputs is recommended after

VDDQ is stable. The inputs of the I/O pins can be applied at the same time as VDDQ as long as Vih (level of

I/O pins) is lower than

VDDQ.

ABSOLUTE MAXIMUM RATINGS AND OPERATING RANGE

A1', A0' = 1,1

0,0

1,0

0,1

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IS61VPS102418B Datasheet(PDF) 10 Page - Integrated Silicon Solution, Inc

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