1

Rev. A

8/4/2014

IS61NLP204836B/IS61NVP/NVVP204836B

IS61NLP409618B/IS61NVP/NVVP409618B

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liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on

any published information and before placing orders for products.

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failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written

assurance to its satisfaction, that:

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FEATURES

• 100 percent bus utilization

• No wait cycles between Read and Write

• Internal self-timed write cycle

• Individual Byte Write Control

• Single R/W (Read/Write) control pin

• Clock controlled, registered address,

data and control

• Interleaved or linear burst sequence control us-

ing MODE input

• Three chip enables for simple depth expansion

and address pipelining

• Power Down mode

• Common data inputs and data outputs

• CKE pin to enable clock and suspend operation

• JEDEC 100-pin TQFP, 165-ball PBGA and 119-

ball PBGA packages

• Power supply:

• JTAG Boundary Scan for PBGA packages

• Industrial temperature available

• Lead-free available

DESCRIPTION

The72Megproductfamilyfeatureshigh-speed,low-power

synchronous static RAMs designed to provide a burstable,

high-performance, 'no wait' state, device for networking

and communications applications. They are organized as

2,096,952 words by 36 bits and 4,193,904 words by 18

bits, fabricated with

Incorporating a 'no wait' state feature, wait cycles are

eliminated when the bus switches from read to write, or

write to read. This device integrates a 2-bit burst counter,

high-speed SRAM core, and high-drive capability outputs

into a single monolithic circuit.

Allsynchronousinputspassthroughregistersarecontrolled

by a positive-edge-triggered single clock input. Operations

may be suspended and all synchronous inputs ignored

when Clock Enable, CKE is HIGH. In this state the internal

device will hold their previous values.

AllRead,WriteandDeselectcyclesareinitiatedbytheADV

input. When the ADV is HIGH the internal burst counter

is incremented. New external addresses can be loaded

when ADV is LOW.

Write cycles are internally self-timed and are initiated

by the rising edge of the clock inputs and when WE is

LOW. Separate byte enables allow individual bytes to be

written.

A burst mode pin (MODE) defines the order of the burst

sequence.WhentiedHIGH,theinterleavedburstsequence

is selected. When tied LOW, the linear burst sequence is

selected.

2M x 36 and 4M x 18

72Mb, PIPELINE 'NO WAIT' STATE BUS SRAM

AUGUST 2014

Symbol

Parameter

250

200

166

Units

Clock Access Time

2.8

3.1

3.8

ns

Cycle Time

4

5

6

ns

Frequency

250

200

166

MHz

FAST ACCESS TIME