IS61NVVP409618B datasheet(4/39 Pages) ISSI

Part #	IS61NVVP409618B

Description	100 percent bus utilization

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Manufacturer	ISSI [Integrated Silicon Solution, Inc]

Direct Link	http://www.issi.com

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Integrated Silicon Solution, Inc. — www.issi.com

Rev. A

8/4/2014

IS61NLP204836B/IS61NVP/NVVP204836B

IS61NLP409618B/IS61NVP/NVVP409618B

Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.

PIN DESCRIPTIONS

Symbol

Pin Name

A

Synchronous Address Inputs

A0, A1

Synchronous Burst Address Inputs

ADV

Synchronous Burst Address Advance/

Load

WE

Synchronous Read/Write Control Input

CLK

Synchronous Clock

CKE

Synchronous Clock Enable

CE

, CE2, CE2 Synchronous Chip Enable

BWa

-BWd

Synchronous Byte Write Inputs

OE

Asynchronous Output Enable

ZZ

Asynchronous Power Sleep

Mode

MODE

Burst Sequence Selection

TCK, TDI

JTAG Pins

TDO, TMS

VDD

Power Supply

NC

No Connect

DQa-DQd

Synchronous Data Inputs/Outputs

DQPa-DQPd

Synchronous Parity Data

Inputs/Outputs

VDDQ

I/O Power Supply

Vss

Ground

PIN CONFIGURATION — 2M x 36, 165-Ball PBGA (TOP VIEW)

1

2

3

4

5

6

7

8

9

10

11

A

NC

A

CE

BW

c

BW

b

CE

2

CKE

ADV

A

NC

B

NC

A

CE2

BW

d

BW

a

CLK

WE

OE

A

NC

C

DQPc

NC

VDDQ

VSS

VDDQ

NC

DQPb

D

DQc

VDDQ

VDD

VSS

VDD

VDDQ

DQb

E

DQc

VDDQ

VDD

VSS

VDD

VDDQ

DQb

F

DQc

VDDQ

VDD

VSS

VDD

VDDQ

DQb

G

DQc

VDDQ

VDD

VSS

VDD

VDDQ

DQb

H

NC

VDD

VSS

VDD

NC

ZZ

J

DQd

VDDQ

VDD

VSS

VDD

VDDQ

DQa

K

DQd

VDDQ

VDD

VSS

VDD

VDDQ

DQa

L

DQd

VDDQ

VDD

VSS

VDD

VDDQ

DQa

M

DQd

VDDQ

VDD

VSS

VDD

VDDQ

DQa

N

DQPd

NC

VDDQ

VSS

NC

VSS

VDDQ

NC

DQPa

P

NC

A

TDI

A1*

TDO

A

NC

R

MODE

A

TMS

A0*

TCK

A

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